P89C738 datasheet(13/64 Pages) PHILIPS

13 / 64 page

Notes

1. To avoid a ‘latch-up’ effect at power-on, the voltage on any pin (at any time) must not be higher than VDD + 0.5 V or lower than VSS − 0.5 V

respectively.

2. To prohibit the toggling of the ALE/WE pin (RFI noise reduction) the bit RFI in the PCON register (PCON.5) must be set by software. This bit is

cleared on reset and can be cleared by software. When set, ALE/WE pin will be pulled down internally, switching an external address latch to a

quiet state. The MOVX instruction will still toggle ALE/WE as a normal MOVX. ALE/WE will retain its normal HIGH value during Idle mode and a

LOW value during Power-down mode while in the ‘RFI’ mode. Additionally during internal access (EA = 1) ALE/WE will toggle normally when the

address exceeds the internal program memory size. During external access (EA = 0) ALE/WE will always toggle normally, whether the flag ‘RFI’ is

set or not.

3. n.a. = not applicable.

P4.0 to P4.7

20, 24,

26, 44,

46, 50, 53

and 57

12, 16,

18, 34,

36, 40, 43

and 47

n.a.(3)

n.a.

Port 4: P4.0 to P4.7; 8-bit quasi-bidirectional I/O port with internal

pull-ups. Port 4 can sink/source 4 LSTTL inputs. It can drive CMOS

inputs without external pull-ups.

P5.0 to P5.7

60, 62,

63, 7, 8,

10, 13

and 16

50, 52,

53, 63,

64, 2, 5

and 8

n.a.

Port 5: P5.0 to P5.7; 8-bit quasi-bidirectional I/O port with internal

pull-ups. Port 5 can sink/source 4 LSTTL inputs. It can drive CMOS

inputs without external pull-ups.

n.c.

1, 4, 18,

31, 32,

33, 35,

36, 37, 38

52 and 66

23, 24,

25, 27,

28, 42

and 58

6, 17, 28

and 39

1, 12, 23

and 34

n.a.

Not connected.

SYMBOL

PIN(1)

DESCRIPTION

PLCC68

QFP64

PLCC44

QFP44

DIP40

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