M750000009 datasheet(83/136 Pages) SPANSION

83 / 136 page

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

ADV ANCE

I N FO RMAT I O N

Refer to the AC AC Characteristics table for timing

specifications and to Figure 13 for the timing diagram.

CC1 in the DC Characteristics table represents the ac-

tive current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V

IL, and OE# to VIH.

For program operations, the BYTE# pin determines

whether the device accepts program data in bytes or

words. Refer to “Requirements for Reading Array

Data” for more information.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once a bank enters the Un-

lock Bypass mode, only two write cycles are required

to program a word or byte, instead of four. The “Word

Program Command Sequence” section has details on

programming data to the device using both standard

and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 2 indicates the address

space that each sector occupies. Similarly, a “sector

address” is the address bits required to uniquely select

a sector. The “Command Definitions” section has de-

tails on erasing a sector or the entire chip, or suspend-

ing/resuming the erase operation.

The device address space is divided into four banks. A

“bank address” is the address bits required to uniquely

select a bank.

CC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The AC

Characteristics section contains timing specification

tables and timing diagrams for write operations.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. This is one of two functions

provided by the WP#/ACC pin. This function is prima-

rily intended to allow faster manufacturing throughput

at the factory.

If the system asserts V

HH on this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the

time required for program operations. The system

would use a two-cycle program command sequence

as required by the Unlock Bypass mode. Removing

HH from the WP#/ACC pin returns the device to nor-

mal operation.

Note that VHH must not be asserted on

WP#/ACC for operations other than accelerated pro-

gramming, or device damage may result. In addition,

the WP#/ACC pin must not be left floating or uncon-

nected; inconsistent behavior of the device may result.

See “Write Protect (WP#)” on page 87 for related infor-

mation.

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ15–DQ0. Standard read cycle timings apply in

this mode. Refer to the Autoselect Mode and Autose-

lect Command Sequence sections for more informa-

tion.

Simultaneous Read/Write Operations with

Zero Latency

This device is capable of reading data from one bank

of memory while programming or erasing in the other

bank of memory. An erase operation may also be sus-

pended to read from or program to another location

with in the same ba nk (except the sector b ein g

erased). Figure 19 shows how read and write cycles

may be initiated for simultaneous operation with zero

latency. I

CC6 and ICC7 in the DC Characteristics table

represent the current specifications for read-while-pro-

gram and read-while-erase, respectively.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V

CC ± 0.3 V.

(Note that this is a more restricted voltage range than

IH.) If CE# and RESET# are held at VIH, but not within

CC ± 0.3 V, the device will be in the standby mode,

but the standby current will be greater. The device re-

quires standard access time (t

CE) for read access

when the device is in either of these standby modes,

before it is ready to read data.

If the device is deselected during erasure or program-

ming , the device draws a ctive current until th e

operation is completed.

CC3 in the DC Characteristics table represents the

standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

this mode when addresses remain stable for t

ACC +

30 ns. The automatic sleep mode is independent of

the CE#, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when ad-

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