M500000013 datasheet(10/70 Pages) SPANSION

10 / 70 page

May 19, 2003

Am50DL9608G

P R E L I M I NARY

ORDERING INFORMATION

The order number (Valid Combination) is formed by the following:

Valid Combinations

Valid Combinations list configurations planned to be supported in vol-

ume for this device. Consult the local AMD sales office to confirm

availability of specific valid combinations and to check on newly re-

leased combinations.

MCP DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is a latch used to store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

The state machine outputs dictate the function of the

device. Tables 1-2 lists the device bus operations, the

inputs and control levels they require, and the result-

ing output. The following subsections describe each of

these operations in further detail.

Am50DL960

TAPE AND REEL

7 inches

13 inches

TEMPERATURE RANGE

Industrial (–40

°C to +85°C)

SPEED OPTION

70 ns Flash + 55 ns pSRAM

70 ns Flash + 70 ns pSRAM (See page 5)

BOOT SECTOR ARCHITECTURE

Top Boot of Am29DL320G Flash

Bottom Boot of Am29DL320G Flash

PROCESS TECHNOLOGY

0.17 µm

PSEUDO SRAM DEVICE DENSITY

8 Mbits

AMD DEVICE NUMBER/DESCRIPTION

Am50DL9608G

Stacked Multi-Chip Package (MCP) Flash Memory and Pseudo SRAM

Am29DL640G 64 Megabit (8/4 M x 16-Bit) and

Am29DL320G 32 Megabit (4/2 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

and 8 Mbit (152 K x 16-Bit) Pseudo Static RAM

Valid Combinations

Order Number

Package Marking

Am50DL9608GT70I

Am50DL9608GB70I

T, S

M500000010

M500000011

Am50DL9608GT75I

Am50DL9608GB75I

T, S

M500000012

M500000013

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