AM29BDS128H datasheet(36/89 Pages) AMD

36 / 89 page

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A TA

SH EE T

Table 14.

Programmable Wait State Settings

Notes:

1. Upon power-up or hardware reset, the default setting is

seven wait states.

2. RDY will default to being active with data when the Wait

State Setting is set to a total initial access cycle of 2.

It is recommended that the wait state command

sequence be written, even if the default wait state value

is desired, to ensure the device is set as expected. A

hardware reset will set the wait state to the default set-

ting.

Reduced Wait-state Handshaking Option

If the device is equipped with the reduced wait-state

handshaking option, the host system should set

address bits A14–A12 to 010 for the system/device to

execute at maximum speed.

Table 15 describes the typical number of clock cycles

(wait states) for various conditions.

Table 15.

Wait States for Reduced Wait-state

Handshaking

Notes:

1. If the latched address is 3Eh or 3Fh (or an address offset

from either address by a multiple of 64), add two access

cycles to the values listed.

2. In the 8-, 16-, and 32-word burst modes, the address

pointer does not cross 64-word boundaries (3Fh, or

addresses offset from 3Fh by a multiple of 64).

3. Typical initial access cycles may vary depending on

system margin requirements.

A14

A13

A12

Total Initial Access

Cycles

000

001

010

011

100

7 (default)

110

Reserved

111

Reserved

System

Frequency

Range

Even Initial

Address

Odd Initial

Address

Device

Speed

Rating

–22 MHz

(54 MHz)

–28 MHz

–43 MHz

–54 MHz

–28 MHz

(66 MHz)

–35 MHz

–53 MHz

–66 MHz

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