L6701TR datasheet(26/44 Pages) STMICROELECTRONICS

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11 Dynamic VID Transitions

L6701

26/44

Dynamic VID Transitions

L6701 is able to manage Dynamic VID Code changes in all its operative modes (VR10, K8 and

also VR9) so allowing Output Voltage modification during normal device operation. PGOOD

(when applicable), OVP and UVP signals are masked during every VID transition and they are

re-activated after the transition finishes with a 32 clock cycles delay to prevent from false

triggering.

When changing dynamically the regulated voltage (D-VID), the system needs to charge or

discharge the output capacitor accordingly. This means that an extra-current

needs to be delivered, especially when increasing the output regulated voltage and it must be

considered when setting the over current threshold. In the previous relationship, dVOUT is the

selected DAC LSB (12.5mV for VR10 DAC or 25mV for both VR9 and K8 DACs) and TVID is

the time interval between each LSB transition (typically externally driven). Overcoming the OC

threshold during the dynamic VID causes the device to enter the constant current limitation

slowing down the output voltage dV/dt also causing the failure in the D-VID test.

Figure 11. Dynamic VID Transitions

L6701 checks for VID code modifications (See Figure 11) on the rising edge of an internal

additional DVID-clock and waits for a confirmation on the following falling edge. Once the new

code is stable, on the next rising edge, the reference starts stepping up or down in LSB

increments every VID-clock cycle until the new VID code is reached. During the transition, VID

code changes are ignored; the device re-starts monitoring VID after the transition has finished

on the next rising edge available. VID-clock frequency (FDVID) depends on the operative mode

selected: for VR10 Mode it is equal to three times the system switching frequency programmed

for each phase (FDVID = 3 x FSW) to assure compatibility with the specifications while, for VR9

and K8, this frequency is lowered to FDVID = FSW.

DVID

–

OUT

OU T dTVI D

⁄

⋅

TDVID

x 4 Step VID Transition

VID [0,5]

Int. Reference

Vout

Tsw

4 x 1 Step VID Transition

TVID

VID Clock

Vout Slope Controlled by internal

DVID-Clock Oscillator

Vout Slope Controlled by external

driving circuit (TVID)

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