DS30669 Rev. 2 - 2

6 of 7

DLP3V3DTZ

www.diodes.com

A07

A07 = Product Type Marking Code

YM = Date Code Marking

Y = Year e.g., T = 2006

M = Month e.g., 1 = Janurary

Date Code Key

Month

Jan

Feb

March

Apr

May

Jun

Jul

Aug

Sep

Oct

Nov

Dec

Code

12

3

4

5

6

7

89

O

N

D

Year

2005

2006

2007

2008

2009

Code

ST

UV

W

Fig. 15

Marking Information

Device

Marking Code

Packaging

Shipping

DLP3V3DTZ-7

A07

SOT-23

3000/Tape & Reel

Notes:

5. For Packaging Details, go to our website at http://www.diodes.com/datasheets/ap02007.pdf.

Protection from ESD

It is a fact that ESD is the primary cause of failure in electronic systems. Transient Voltage Suppressors(TVS) are an ideal choice for using as

ESD protection devices. They have the capability to clamp the incoming transient to such a low level that the damage to the circuit beyond the

device is prevented. Surface mount TVS are the best choice for minimum lead inductance. DLP3V3DTZ is designed to be used as two

uni-directional or single bi-directional protection device in a circuit.They serve as parallel protection elements, connected between the signal

line to ground. It will present a high impedance to the protected line up to 3.3 volts. As the transient rises above the operating voltage which is

the breakdown voltage of the device, the TVS diode becomes a low impedance path diverting the transient current to ground.

Dynamic Resistance to Calculate Clamping Voltage

parameters is listed here. The voltage across the protected circuitry can be calculated as following:

Where Ipp is the peak current through the TVS Diode. The short duration of the ESD has led us to a widely adapted classical test wave, 8/20

mS and 10/1000 mS surges. Since Zzt remains stable for a surge duration less than 20mS, the 2.5 mS rectangular surge is sufficient for use.

Peak Pulse Power Calculation

The following relation fits well for pulse width less than 10 mS.

e.g. Ppp = 372 watts for pulse width(td) of 20

Now, Ppp when td= 50

Tips for Circuit Board Layout

Correct layout of the circuit board plays a critical role in preventing ESD induced failures. Some of useful guidelines are given below:

- Trace length between the TVS diode and the circuit or line to be protected should be kept to a minimum.

- Always place a TVS diode as close as possible to the input terminals or connectors if one is required.

- Try to avoid or minimize power and ground loops or any other conductive loops.

- Try to use ground planes whenever feasible rather than a simple ground trace.

- The path to ground for the ESD transient return should be as short as possible.

Application Information