Application Notes

Direct capacitive loading reduces the phase margin of amplifiers and this results in ringing or

even oscillation. Applications that require greater capacitive drive capability should use an

isolation resistor between the output and the capacitive load like the circuit in Figure 14. The

isolation resistor RISO and the load capacitor CL form a zero to increase stability. The bigger

the RISO resistor value, the more stable VOUT will be. Note that this method results in a loss of

gain accuracy because RISO forms a voltage divider with the RL.

Fig. 14 Indirectly Driving Heavy Capacitive Load

An improvement circuit is shown in Figure 15. It provides DC accuracy as well as AC

stability. The RF provides the DC accuracy by connecting the inverting signal with the output.

The CF and RISO serve to counteract the loss of phase margin by feeding the high frequency

component of the output signal back to the amplifier’s inverting input, thereby preserving

phase margin in the overall feedback loop.

Fig. 15 Indirectly Driving Heavy Capacitive Load with DC Accuracy

For no-buffer configuration, there are two other ways to increase the phase margin: (a)

by increasing the amplifier’s gain, or (b) by placing a capacitor in parallel with the feedback

resistor to counteract the parasitic capacitance associated with inverting node.

Power Supply Layout And Bypass

The LMV72xA family operates from either a single +2.5V to +5.5V supply or

dual

±1.25V to ±2.25V supplies. For single-supply operation, bypass the power supply VS

with a ceramic capacitor (i.e. 0.01μF to 0.1μF) which should be placed close (within 2mm

for good high frequency performance) to the VS pin. For dual-supply operation both the VS+

and the

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10MHz, RRIO CMOS Operational Amplifiers

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