USB97C201 datasheet(32/59 Pages) SMSC

32 / 59 page

SMSC USB97C201

Page 32

Rev. 11-05-03

DATASHEET

Table 30 – USB Configuration Number Register

USB_CONF

(0xAD - RESET=0x00)

USB CONFIGURATION NUMBER REGISTER

BIT

NAME

R/W

DESCRIPTION

[7:4]

Reserved

Always returns a “0”.

{3:0}

CONFIG

Reflects

the

current

configuration

number

the

USB97C201 system as set by the host.

Table 31 – Endpoint 0 Receive Control Register

EP0RX_CTL

(0xAF - RESET=0x00)

ENDPOINT 0 RECEIVE CONTROL REGISTER

BIT

NAME

R/W

DESCRIPTION

[7:4]

Reserved

This bit always reads “0”.

DTOG

This bit reflects the data toggle state of the last received

data token.

STALL

R/W

When set to a “1”, EP0 will respond with the STALL

handshake to OUT tokens EXCEPT a SETUP, which it will

ACK unconditionally. Either the internal SIE or the user may

set this bit. Receipt of a SETUP packet or USB RESET

clears this bit. Writing a “0” to this bit has no effect.

Reserved

This bit always reads “0”.

ENABLE

Reads 1 if EP0 Receive is enabled by SIE.

Table 32 – Endpoint 0 Transmit Control Register

EP0TX_CTL

(0xB1 - RESET=0x00)

ENDPOINT 0 TRANSMIT CONTROL REGISTER

BIT

NAME

R/W

DESCRIPTION

Reserved

This bit always reads “0”.

Reserved

This bit always reads “0”.

Reserved

This bit always reads “0”.

R/W

When written with a “1”, allows the SIE to transfer data from

the buffer SRAM to EP0. OUT tokens will be NAK’d until the

transfer has been completed. It is cleared by the SIE when

transmission of the packet has been completed.

Reserved

This bit always reads “0”.

STALL

R/W

When set to a “1”, EP0 TX will respond with the STALL

handshake to IN tokens. . Either the internal SIE or the user

may set this bit. Receipt of a SETUP packet or USB RESET

clears this bit. Writing a “0” to this bit has no effect.

Reserved

This bit always reads “0”.

ENABLE

Reads “1” if EP0 Transmit is enabled by the SIE.

Table 33 – Endpoint 1 Receive Control Register

EP1RX_CTL

(0xB2 - RESET=0x00)

ENDPOINT 1 RECEIVE CONTROL REGISTER

BIT

NAME

R/W

DESCRIPTION

[7:4]

Reserved

This bit always reads “0”.

DTOG

This bit reflects the data toggle state of the last received

data token.

STALL

R/W

When set to a “1”, EP1 RX will respond with the STALL

handshake to OUT tokens. . Either the internal SIE or the

user may set this bit. Receipt of a “CLEAR FEATURE

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