LPC47M172 datasheet(9/226 Pages) SMSC

9 / 226 page

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

SMSC/Non-SMSC Register Sets (Rev. 01-11-07)

Page 9

SMSC LPC47M172

DATASHEET

Table 7.10 - I/O Address Map ....................................................................................................................................114

Table 7.11 - Host Interface Flags ...............................................................................................................................115

Table 7.12 - Status Register ......................................................................................................................................117

Table 7.13 - Keyboard and Mouse Pin/Register Reset Values ..................................................................................118

Table 7.14 - Keyboard Port 92 Register.....................................................................................................................119

Table 7.15 - nA20M Truth Table ................................................................................................................................120

Table 7.16 - GPIO Summary......................................................................................................................................124

Table 7.17 - General Purpose I/O Port Assignments .................................................................................................125

Table 7.18 - GPIO Configuration Summary ...............................................................................................................125

Table 7.19 - GPIO Read/Write Behavior ....................................................................................................................126

Table 7.20 - Hard Drive Front Panel Pins ..................................................................................................................131

Table 7.21 - nHD_LED Truth Table............................................................................................................................131

Table 7.22 - LED Pins ................................................................................................................................................132

Table 7.23 - LED Truth Table.....................................................................................................................................132

Table 7.24 - Reference Generation Pins ....................................................................................................................133

Table 7.25 - REF5V ...................................................................................................................................................134

Table 7.26 - REF5V_STBY ........................................................................................................................................134

Table 7.27 - nIDE_RSTDRV Pin ................................................................................................................................135

Table 7.28 - nIDE_RSTDRV Truth Table ...................................................................................................................135

Table 7.29 - nPCIRST_OUT Pins ..............................................................................................................................136

Table 7.30 - nPCIRST_OUT and nPCIRST_OUT2 Truth Table ................................................................................136

Table 7.31 - Voltage Translation DDC Pins ...............................................................................................................136

Table 7.32 - VGA DDCSDA Voltage Translation Logic ..............................................................................................137

Table 7.33 - VGA DDCSCL Voltage Translation Logic ..............................................................................................137

Table 7.34 - SMBus Isolation Pins .............................................................................................................................138

Table 7.35 - SMB_CLK Isolation Logic ......................................................................................................................139

Table 7.36 - SMB_DAT Isolation Logic ......................................................................................................................139

Table 7.37 - nPS_ON, nCPU_PRESENT and nSLP_S3 Pins ...................................................................................140

Table 7.38 - nPS_ON Truth Table..............................................................................................................................140

Table 7.39 - PWRGD_3V, nFPRST and PWRGD_PS Pins .......................................................................................140

Table 7.40 - PWRGD_3V Truth Table........................................................................................................................141

Table 7.41 - SCK_BJT_GATE Pin .............................................................................................................................142

Table 7.42 - SCK_BJT_GATE Truth Table ................................................................................................................142

Table 7.43 - nBACKFEED_CUT and LATCHED_BF_CUT Pins ................................................................................143

Table 7.44 - nBACKFEED_CUT Truth Table .............................................................................................................143

Table 7.45 - LATCHED_BF_CUT Truth Table ...........................................................................................................144

Table 7.46 - Latched Backfeed Cut Power Up Sequence Timing ..............................................................................145

Table 7.47 - Latched Backfeed Cut Sequence 1 and 2 Timing ..................................................................................146

Table 7.48 - nRSMRST Pin........................................................................................................................................148

Table 7.49 - CNR Pins ...............................................................................................................................................148

Table 7.50 - CNR Logic Truth Table ..........................................................................................................................149

Table 8.1 - Power Control Runtime Registers Summary, LD_NUM Bit = 0................................................................150

Table 8.2 - Power Control Runtime Registers Description, LD_NUM Bit = 0 .............................................................151

Table 9.1 - GPIO Runtime Registers Summary, LD_NUM = 0...................................................................................157

Table 9.2 - GPIO Runtime Registers Description, LD_NUM = 0 ................................................................................158

Table 10.1 - Runtime Register Block Runtime Registers Summary ...........................................................................161

Table 10.2 - Runtime Register Block Runtime Registers Description ........................................................................162

Table 11.1 - LPC47M172 Configuration Registers Summary, LD_NUM bit = 0 .........................................................175

Table 11.2 - LPC47M172 Configuration Register Summary, LD_NUM=1..................................................................177

Table 11.3 - Chip Level Registers ..............................................................................................................................179

Table 11.4 - Logical Device Registers........................................................................................................................182

Table 11.5 - Primary Interrupt Select Configuration Register Description ..................................................................184

Table 11.6 - DMA Channel Select Configuration Register Description ......................................................................184

Table 11.7 - Logical Device I/O Address, LD_NUM Bit = 0 ........................................................................................186

Table 11.8 - Logical Device I/O Address, LD_NUM Bit = 1 .......................................................................................187

Table 11.9 - Floppy Disk Controller Logical Device Configuration Registers .............................................................189

Table 11.10 - Serial Port 2 Logical Device Configuration Registers...........................................................................190

Table 11.11 - Parallel Port Logical Device Configuration Registers ...........................................................................191

Table 11.12 - Serial Port 1 Logical Device Configuration Registers...........................................................................192

Table 11.13 - Keyboard Logical Device Configuration Registers ...............................................................................193

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