EMC6D103S datasheet(39/84 Pages) SMSC

39 / 84 page

Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features

Datasheet

SMSC EMC6D103S

Revision 0.2 (06-14-06)

DATASHEET

Figure 7.6 Illustration of PWM Ramp Rate Control

Notes:

The PWM Duty Cycle latches the Ramping Duty Cycle on the rising edge of the PWM output.

The calculated duty cycle, ramping duty cycle, and the PWM output duty cycle are asynchronous

to each other, but are all synchronized to the internal 90kHz clock source.

001

17.6

26.52

104 msec

9.62

010

11.8

17.595

69 msec

14.49

011

7.0

10.455

41 msec

24.39

100

4.4

6.63

26 msec

38.46

101

3.0

4.59

18 msec

55.56

110

1.6

2.55

10 msec

100

111

0.8

1.275

5 msec

200

Table 7.1 PWM Ramp Rate (continued)

RRX-[2:0]

PWM RAMP TIME (SEC)

(TIME FROM 33%

DUTY CYCLE TO

100% DUTY CYCLE)

PWM RAMP TIME (SEC)

(TIME FROM MIN DUTY

CYCLE TO 100% DUTY

CYCLE)

TIME PER

PWM STEP

(PWM STEP SIZE =

1/255)

PWM

RAMP

RATE

(HZ)

Example 1: PWM period < Ramp Rate Step Size

PWM frequency = 87.7Hz (11.4msec) & PWM Ramp Rate = 38.46Hz (26msec)

Calculate Duty Cycle

70h

74h

PWM Duty Cycle

70h

11.4ms

71h

72h

73h

74h

Example 2: PWM period > Ramp Rate Step Size

PWM frequency = 11Hz (90.9msec) & PWM Ramp Rate = 38.46Hz (26msec)

Calculate Duty Cycle

70h

74h

Ramping Duty Cycle

PWM Duty Cycle

70h

71h

72h

73h

74h

26ms

Ramping Duty Cycle

70h

71h

72h

73h

74h

26ms

90.9msec

71h

74h

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