CA3318CE datasheet(12/12 Pages) INTERSIL

12 / 12 page

Reducing Power

Most power is consumed while in the auto-balance state.

When operating at lower than 15MHz clock speed, power

can be reduced by stretching the sample (

φ2) time. The con-

straints are a minimum balance time (

φ1) of 33ns, and a

maximum sample time of 500ns. Longer sample times cause

droop in the auto-balance capacitors. Power can also be

reduced in the reference string by switching the reference on

only during auto-balance.

Clock Input

The Clock and Phase inputs feed buffers referenced to

VAA+ and VAA-. Phase should be tied to one of these two

potentials, while the clock (if DC coupled) should be driven

at least from 0.2 to 0.7 x (VAA+ - VAA-). The clock may also

be AC coupled with at least a 1VP-P swing. This allows TTL

drive levels or 5V QMOS levels when VAA+ is greater than

5V.

TABLE 1. OUTPUT CODE TABLE

CODE

DESCRIPTION

(NOTE 1)

INPUT VOLTAGE

BINARY OUTPUT CODE

DECIMAL

COUNT

VREF

6.40V (V)

VREF

5.12V (V)

MSB

LSB

Zero

0.00

000000000

1 LSB

0.025

0.02

000000001

2 LSB

0.05

0.04

000000010

•

4 Full Scale

1.60

1.28

001000000

•

2 Full Scale - 1 LSB

3.175

2.54

001111111

127

2 Full Scale

3.20

2.56

010000000

128

2 Full Scale + 1 LSB

3.225

2.58

010000001

129

•

4 Full Scale

4.80

3.84

011000000

192

•

Full Scale - 1 LSB

6.35

5.08

011111110

254

Full Scale

6.375

5.10

011111111

255

Over Flow

6.40

5.12

111111111

511

NOTE: 1. The voltages listed above are the ideal centers of each output code shown as a function of its associated reference voltage.

CA3318

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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.

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