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PCA9538DBRG4 bảng dữ liệu(PDF) 7 Page - Texas Instruments

tên linh kiện PCA9538DBRG4
Giải thích chi tiết về linh kiện  REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
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Register Descriptions
Power-On Reset
RESET Input
PCA9538
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
SCPS126D – SEPTEMBER 2006 – REVISED MARCH 2007
The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is
defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these
registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the
Input Port register will be accessed next.
Register 0 (Input Port Register) Table
BIT
I7
I6
I5
I4
I3
I2
I1
I0
DEFAULT
X
X
X
X
X
X
X
X
The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Register 1 (Output Port Register) Table
BIT
O7
O6
O5
O4
O3
O2
O1
O0
DEFAULT
1
1
1
1
1
1
1
1
The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration
register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this
register is cleared (written with a 0), the corresponding port pin original polarity is retained.
Register 2 (Polarity Inversion Register) Table
BIT
N7
N6
N5
N4
N3
N2
N1
N0
DEFAULT
0
0
0
0
0
0
0
0
The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,
the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output.
Register 3 (Configuration Register) Table
BIT
C7
C6
C5
C4
C3
C2
C1
C0
DEFAULT
1
1
1
1
1
1
1
1
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9538 in a reset condition
until VCC has reached VPOR. At that point, the reset condition is released and the PCA9538 registers and
SMBus/I2C state machine will initialize to their default states. After that, VCC must be lowered to below 0.2 V and
then back up to the operating voltage for a power-reset cycle.
The RESET input can be asserted to reset the system while keeping the VCC at its operating level. A reset can
be accomplished by holding the RESET pin low for a minimum of tW. The PCA9538 registers and I
2C/SMBus
state machine are changed to their default states once RESET is low (0). Once RESET is high (1), the I/O levels
at the P port can be changed externally or through the master. This input requires a pullup resistor to VCC if no
active connection is used.
7
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