CX20921 AudioSmart Data Sheet

Integrated Interchip Sound (I2S)

Conexant Confidential

03/11/15

001DSR01

24

Left-Justified Mode

Left-justified timing uses the WS clock to define when the data being transmitted is for the left channel or

the right channel. The WS is high for the left channel, and low for the right channel (requires the WS

polarity control bit to be set to 1). A bit clock running at a minimum of 2 x sample width x sample frequency

is used to clock the data. The first data bit appears on the data lines at the same time WS toggles. The

data is written MSB first, and is valid on the rising edge of bit clock. When the programmed sample width is

taken, any remaining bits are ignored. If the WS toggles before the full word length is read, the remaining

bits are zeroed.

Figure 13: Left-Justified Timing Diagram

Right-Justified Mode

Right-justified timing uses the WS clock to define whether the data is being transmitted for the left channel

or right channel. The WS is high for the left channel, and low for the right channel (requires the WS polarity

control bit to be set to 1). A bit clock running at a minimum of 2 x sample width x sample frequency is used

to clock the data. Data is captured in a 24-bit shift register until the WS toggles. When the WS toggles the

last 24 bits, 16 bits or 8 bits are transferred to the channel indicated by the previous state of WS. In right-

justified mode, the LSB of data is always clocked by the last bit clock before the WS transitions. The data

is written MSB first and is valid on the rising edge of bit clock. All leading bits are ignored.

Figure 14: Right-Justified Timing Diagram