CC1010-RTY1 datasheet(31/152 Pages) TI

31 / 152 page

CC1010

SWRS047

Page 31 of 152

15.6.3

Interrupt Priority

Interrupts are prioritised in two stages:

Interrupt level and natural priority. The

interrupt level (low, high or highest) takes

precedence over the natural priority.

The Flash / Debug Interrupt, if enabled,

always has the highest priority and is the

only interrupt that can have the highest

priority. All other interrupts can be

assigned either low or high priority, set by

the registers IP and EIP listed below.

Two interrupts with the same interrupt

priority that occur simultaneously are

resolved through their natural priority. The

natural priority is shown in Table 13. The

interrupt having the lowest natural priority

will be serviced first.

Once an interrupt is being serviced, only

an interrupt of higher priority level can

interrupt the service routine of the interrupt

currently being serviced.

IP (0xB8) - Interrupt Priority Register

Bit

Name

R/W

Reset value

Description

Reserved, read as 1

PS1

R/W

Serial Port 1 interrupt priority control

0 : Interrupt has low priority

1 : Interrupt has high priority

R/W

Reserved for future use

PS0

R/W

Serial Port 0 interrupt priority control

0 : Interrupt has low priority

1 : Interrupt has high priority

PT1

R/W

Timer 1 interrupt priority control

0 : Interrupt has low priority

1 : Interrupt has high priority

PX1

R/W

External Interrupt 1 (from

P3.3) interrupt priority control

0 : Interrupt has low priority

1 : Interrupt has high priority

PT0

R/W

Timer 0 interrupt priority control

0 : Interrupt has low priority

1 : Interrupt has high priority

PX0

R/W

External Interrupt 0 (from

P3.2) interrupt priority control

0 : Interrupt has low priority

1 : Interrupt has high priority

EIP (0xF8) - Extended Interrupt Priority Register

Bit

Name

R/W

Reset value

Description

Reserved, read as 1

PRTC

R/W

Realtime Clock interrupt priority control

0 : Interrupt has low priority

1 : Interrupt has high priority

PT3

R/W

Timer 3 interrupt priority control

0 : Interrupt has low priority

1 : Interrupt has high priority

PAD

R/W

ADC / DES interrupt priority control

0 : Interrupt has low priority

1 : Interrupt has high priority

PT2

R/W

Timer 2 interrupt priority control

0 : Interrupt has low priority

1 : Interrupt has high priority

PRF

R/W

0 : Interrupt has low priority

1 : Interrupt has high priority

CC1010-RTY1 bảng dữ liệu(PDF) 31 Page - Texas Instruments

CC1010-RTY1 bảng dữ liệu(HTML) 31 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL