1999 November

3

Philips Semiconductors

Product specification

Full Frame CCD Image Sensor

FTF3020-C

Architecture of the FTF3020-C

The optical centres of all pixels in the image section form a square

grid. The charge is generated and integrated in this section. Output

registers are located below and above the image section for read-

out. After the integration time, the image charge is shifted one line

at the time to either the upper or lower register or to both

simultaneously, depending on the read-out mode. The left and the

right half of each register can be controlled independently. This

enables either single or multiple read-out. During vertical transport,

the C3 gates separate the pixels in the register. The central C3 gates

of the lower and upper registers are part of the left half of the sensor

(W and Z quadrants respectively). Each register can be used for

vertical binning. Each register contains a summing gate at both ends

that can be used for horizontal binning (see figure 2).

OUTPUT REGISTERS

Output buffers on each corner

Number of registers

Number of dummy cells per register

Number of register cells per register

Output register horizontal transport clock pins

Capacity of each C-clock phase

Overlap capacity between neighbouring C-clocks

Output register Summing Gates

Capacity of each SG

Reset Gate clock phases

Capacity of each RG

Three-stage source follower

2

14 (2x7)

3134 (3120+14)

6 pins per register (C1..C3)

200 pF per pin

40pF

4 pins (SG)

15pF

4 pins (RG)

15pF

IMAGE SECTION

Image diagonal (active video only)

Aspect ratio

Active image width x height

Pixel width x height

Geometric fill factor

Image clock pins

Capacity of each clock phase

Number of active lines

Number of black reference lines

Number of dummy black lines

Total number of lines

Number of active pixels per line

Number of overscan (timing) pixels per line

Number of black reference pixels per line

Total number of pixels per line

44.30 mm

3:2

36.864 x 24.576 mm

2

12x12 µm

2

80%

16 pins (A1..A4)

7.5nF per pin

2048

4 (=2x2)

8 (=2x4)

2060

3072

8 (2x4)

40 (2x20)

3120