CBT3384PW datasheet(4/10 Pages) PHILIPS

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Philips Semiconductors

Product data

CBT3384

10-bit bus switch with 5-bit output enables

2001 Dec 20

DC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

Tamb = –40 to +85 °C

UNIT

Min

Typ1

Max

VIK

Input clamp voltage

VCC = 4.5 V; II = –18 mA

—

–1.2

Input leakage current

VCC = 5.5 V; VI = GND or 5.5 V

—

±1

µA

ICC

Quiescent supply current2

VCC = 5.5 V; IO = 0, VI = VCC or GND

—

µA

∆ICC

Additional supply current per input pin2

VCC = 5.5 V, one input at 3.4 V, other inputs at VCC

or GND

—

2.5

Control pins

VI = 3.0 V or 0

—

CI(OFF)

Port off capacitance

VO = 3.0 V or 0, OE = VCC

—

VCC = 4.5 V; VI = 0 V; II = 64 mA

—

ron3

On-resistance

VCC = 4.5 V; VI = 0 V; II = 30 mA

—

Ω

VCC = 4.5 V; VI = 2.4 V; II = –15 mA

—

Pass voltage

VI = VCC = 5.0 V; IO = –100 µA

3.4

3.6

3.9

IUCP

Undershoot static current protection

VCC = 5.0 V, IB = 400 µA; OE = 5.0 V; VB ≥ 3.0 V

—

NOTES:

1. All typical values are at VCC = 5 V, Tamb = 25 °C

2. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

3. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is

determined by the lowest voltage of the two (A or B) terminals.

AC CHARACTERISTICS

GND = 0 V; tR; CL = 50 pF

FROM

LIMITS

SYMBOL

PARAMETER

FROM

(INPUT)

(OUTPUT)

VCC = +5.0 V ±0.5 V

UNIT

(INPUT)

(OUTPUT)

Min

Max

tpd

Propagation delay1

A or B

B or A

—

.25

ten

Output enable time

to High and Low level

A or B

1.0

5.7

tdis

Output disable time

from High and Low level

A or B

1.0

5.2

NOTE:

1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on–state

resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).

LIMITS

SYMBOL

PARAMETER DESCRIPTION

Tamb = –40 to +85 °C

VCC = 5 V, ±0.5 V

UNIT

MIN.

MEAN

MAX.

tpd

Propagation delay (see Note 1)

—

250

tPZH

Output enable time to High level

1.6

3.4

5.6

tPHZ

Output enable time from High level

1.7

3.3

5.5

tPZL

Output enable time to Low level

2.3

tPLZ

Output enable time from Low level

2.5

4.5

6.6

NOTE:

1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state

resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance); at +25

°C.

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