6.5 Insulation Specification

Over free-air temperature range and VDD = 2.3 V to 5.5 V (unless otherwise noted); Typical specifications are at TA = 25°C

and VDD = 3.3 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VALUE

UNIT

GENERAL

CLR

External Clearance(1)

Shortest terminal-to-terminal distance through air

>4

mm

CPG

External Creepage(1)

Shortest terminal-to-terminal distance across the package

surface

>4

mm

DTI

Distance through the insulation

Minimum internal gap (internal clearance)

>17

µm

CTI

Comparative tracking index

DIN EN 60112; IEC 60112

>400

V

Material Group

II

Overvoltage category

Rated mains voltage ≤ 150 VRMS

I-IV

Rated mains voltage ≤ 300 VRMS

I-III

DIN EN IEC 60747-17 (VDE 0884-17)

VIORM

Maximum repetitive peak isolation

voltage

At AC voltage

707

VPK

VIOWM

Maximum-rated isolation working

voltage

At AC voltage (sine wave)

500

VRMS

At DC voltage

707

VDC

VIOTM

Maximum transient isolation voltage

VTEST = VIOTM, t = 60 s (qualification test),

VTEST = 1.2 × VIOTM, t = 1 s (100% production test)

4250

VPK

VIMP

Maximum impulse voltage(2)

Tested in air, 1.2/50-μs waveform per IEC 62368-1

TBD

VPK

VIOSM

Maximum surge isolation voltage(4)

Tested in oil (qualification test),

1.2/50-μs waveform per IEC 62368-1

7800

VPK

qpd

Apparent charge(4)

Method a, after input/output safety test subgroups 2 and 3,

Vpd(ini) = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM, tm = 10 s

≤ 5

pC

Method a, after environmental tests subgroup 1,

Vpd(ini) = VIOTM, tini = 60 s, Vpd(m) = 1.3 × VIORM, tm = 10 s

≤ 5

Method b1, at preconditioning (type test) and routine test,

Vpd(ini) = VIOTM, tini = 1 s, Vpd(m) = 1.5 × VIORM, tm = 1 s

≤ 5

Method b2, at routine test (100% production)(6),

Vpd(ini) = VIOTM = Vpd(m); tini = tm = 1 s

≤ 5

CIO

Barrier capacitance,

input to output(5)

VIO = 0.5 VPP at 1 MHz

TBD

pF

RIO

Insulation resistance,

input to output(5)

VIO = 500 V at TA = 25°C

TBD

Ω

VIO = 500 V at 100°C ≤ TA ≤ 125°C

TBD

VIO = 500 V at TA = 150°C

TBD

Pollution degree

2

Climatic category

55/125/21

UL1577

VISO

Withstand isolation voltage

VTEST = VISO, t = 60 s (qualification);

VTEST = 1.2 × VISO, t = 1 s (100% production)

3000

VRMS

(1)

Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Take care

to maintain the creepage and clearance distance of the board design to make sure that the mounting pads of the isolator on the

printedcircuit board do not reduce this distance. Creepage and clearance on a printed circuit board become equal in certain cases.

Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.

(2)

Testing is carried out in air to determine the surge immunity of the isolation barrier.

(3)

Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.

(4)

Apparent charge is electrical discharge caused by a partial discharge (pd).

(5)

All pins on each side of the barrier tied together creating a two-terminal device.

(6)

Either method b1 or b2 is used in production

ISOTMP35

SNIS232 – OCTOBER 2023

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