DSP56F803 datasheet(37/57 Pages) FREESCALE

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56F803 Technical Data, Rev. 16

Freescale Semiconductor

Figure 3-11 External Bus Asynchronous Timing

3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and

T = Clock Period. For 80MHz operation, T = 12.5ns.

Parameters listed are guaranteed by design.

To calculate the required access time for an external memory for any frequency < 80Mhz, use this formula:

Top = Clock period @ desired operating frequency

WS = Number of wait states

Memory Access Time = (Top*WS) + (Top- 11.5)

Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing 1, 5

Operating Conditions: V

SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF

Characteristic

Symbol

Min

Max

Unit

See Figure

RESET Assertion to Address, Data and Control

Signals High Impedance

tRAZ

—21

Figure 3-12

Minimum RESET Assertion Duration2

OMR Bit 6 = 0

OMR Bit 6 = 1

tRA

275,000T

128T

—

Figure 3-12

RESET De-assertion to First External Address Output

tRDA

33T

34T

Figure 3-12

A0–A15,

PS, DS

(See Note)

D0–D15

Note: During read-modify-write instructions and internal instructions, the address lines do not change state.

Data In

Data Out

tAWR

tARDA

tARDD

tRDA

tRD

tRDRD

tRDWR

tWRWR

tWR

tDOS

tWRD

tWRRD

tAD

tDOH

tDRD

tRDD

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