BL702SLASH704SLASH706 datasheet(15/47 Pages) BOUFFALOALB

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BL702/704/706 Datasheet

2.10.1 GPIO

BL702 includes 15 GPIOs, BL704 includes 23 GPIOs, BL706 includes 31 GPIOs, and each GPIO can be used as a

general-purpose input and output function. The pull-up/pull-down/floating can be configured by software. Each GPIO

supports interrupt function, interrupt supports rising edge trigger, falling edge trigger, high level trigger and low level

trigger.

Each GPIO can be set to a high impedance state for power saving in low power consumption mode.

2.10.2 UART

Built-in 2 UARTs (UART0 and UART1), and support LIN master/slave function. The working clock of the UART

module can be selected as FCLK or 96M, and the maximum baud rate is 8M. Support hardware CTS and RTS signal

management. TX and RX have independent FIFOs with a FIFO depth of 128 bytes and support DMA functions.

2.10.3 SPI

One SPI interface, which can be configured as master mode or slave mode, and the SPI module clock is BCLK. As

a master, the maximum SPI Clock can reach 36MHz. As a slave, the maximum SPI Clcok of the master is 24MHz.

The bit width of each frame can be configured as 8 bits/16 bits/24 bits/32 bits.

The transmission and reception of SPI has independent FIFO, and the FIFO depth is fixed to 4 frames (that is, if the

bit width of the frame is 8 bits, the depth of the FIFO is 4 bytes), and the DMA function is supported.

2.10.4 I2C

One I2C interface, support host mode and 7 bit addressing, I2C module clock is BCLK, support standard and fast

mode. With device address register, register address register, the length of the register address can be configured

as 1 byte/2 bytes/3 bytes/4 bytes.

The I2C transceiver has an independent FIFO, the FIFO depth is 2 words, and it supports DMA function.

2.10.5 I2S

One I2S interface, support Left-justified/Right-justified/DSP and other data formats, support 8/16/24/32 bit data width,

in addition to mono/dual-channel mode, support four-channel mode at the same time.

The I2S transceiver has an independent FIFO, and the FIFO depth is 16 frames. When the data width is 16 bits,

the FIFO depth can be set to 32 frames. The I2S module has an independent Audio PLL, and supports two types of

sampling rates of 48K (and its integer frequency division) and 44.1K (and its integer frequency division).

BL702/704/706 Datasheet

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