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DS1207 bảng dữ liệu(PDF) 3 Page - Dallas Semiconductor

tên linh kiện DS1207
Giải thích chi tiết về linh kiện  Time Key
PDF  17 Pages
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nhà sản xuất  DALLAS [Dallas Semiconductor]
Trang chủ  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS1207 bảng dữ liệu(HTML) 3 Page - Dallas Semiconductor

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DS1207
021798 3/17
properly loaded with the function code for stopping the
oscillator. The stop oscillator command consists of the
24-bit command word only (see Figure 10). This com-
mand will only execute prior to issuing a lock command.
After the lock command is issued, stop oscillator com-
mands are ignored.
A sequence for properly setting the expiration time of
the DS1207 is as follows (see Figure 11). First, program
the identification and security match bits to the desired
value. Use normal mode operation to write the appropri-
ate secure data. Second, write the number days remain-
ing register to the desired value. This number can be im-
mediately verified by reading the number of days
remaining. Next, arm the oscillator by writing the appro-
priate command. Then do a normal mode read. This ac-
tion will start the internal oscillator. Now read the 20-bit
day clock counter several times to verify that the oscilla-
tor is running. After oscillator activity has been verified,
issue the stop oscillator command. The lock command
should be issued, followed by the arm oscillator com-
mand. The TimeKey will start the countdown to expira-
tion on the next access. To guarantee security, a locked
TimeKey cannot be unlocked. The key cannot be re-
programmed after expiration. The oscillator verification
portion of this sequence is not required and can be de-
leted when speed in setting time remaining is important.
COMMAND WORD
Each data transfer for normal and program mode begins
with a 3-byte command word as shown in Figure 12. As
defined, the first byte of the command word specifies the
function code. Eight function codes are acceptable
(Figure 13). If any one of the bits of the first byte of the
command word fails to meet one of the exact patterns
for function codes, the data transfer will be aborted.
The first two bits of the second byte of the command
word specify whether the data transfer to follow is pro-
gram or normal mode. The bit pattern for program mode
is 0 in bit 0 and 1 in bit 1. The bit pattern for normal mode
is a 1 in bit 0 and a 0 in bit 1. The other two possible com-
binations for the first two bits of byte 2 will cause the
transfer to abort. The program mode can be invoked
with one of seven function codes: program identification
and security match, read the 20-bit day clock counter,
read the number of days count, write the number of days
count, lock number of days count, arm oscillator, and
stop oscillator.
The remaining six bits of byte 2 and the first four bits of
byte 3 must be written to match one of the five patterns
as indicated in Figure 12 or data transfer will abort. Un-
der special contract with Dallas Semiconductor, these
bits can be defined by the user as any bit pattern other
than those specified as unavailable. The bit pattern as
defined by the user must be written exactly or data
transfer will abort. The last four bits of byte 3 of the com-
mand word must be written 1011 or data transfer will
abort. Table 1 provides a summary of the command
words in hexadecimal as they apply to all function codes
for both program mode and normal mode.
RESET AND CLOCK CONTROL
All data transfers are initiated by driving the RST input
high. The reset input serves three functions. First, it
turns on control logic which allows access to the com-
mand register for the command sequence. Second, the
RST signal provides a power source for the cycle to fol-
low. To meet this requirement, a drive source for RST of
2 mA at 3.5 volts is required. Third, the RST signal pro-
vides a method of terminating data transfer.
A clock cycle is a sequence of a falling edge followed by
a rising edge. For data inputs, the data must be valid
during the rising edge of the clock cycle. Command bits
and data bits are input on the rising edge of the clock.
Data bits are output on the falling edge of the clock. The
rising edge of the clock returns the DQ pin to a high im-
pedance state. All data transfer terminates if the RST
pin is low and the DQ pin goes to a high impedance
state. Data transfer is illustrated in Figure 14 for normal
mode and Figure 15 for program mode.
TIMEKEY CONNECTIONS
The TimeKey is designed to be plugged into a standard
5-pin 0.1 inch center SIP receptacle. A guide is provided
to prevent the TimeKey from being plugged in back-
wards and aid in alignment of the receptacle. For porta-
ble applications, contact to the TimeKey pins can be de-
termined to ensure connection integrity before data
transfer begins. CLK, RST, and DQ all have 20K ohm
pulldown resistors to ground that can be sensed by a
reading device.



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