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SY10E151 bảng dữ liệu(PDF) 1 Page - Micrel Semiconductor |
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SY10E151 bảng dữ liệu(HTML) 1 Page - Micrel Semiconductor |
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1 / 4 page ![]() 1 SY10E151 SY100E151 Micrel, Inc. M9999-032006 hbwhelp@micrel.com or (408) 955-1690 s 1100MHz toggle frequency s Extended 100E VEE range of –4.2V to –5.46V s Differential outputs s Asynchronous Master Reset s Dual clocks s Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75K Ω input pulldown resistors s Fully compatible with Motorola MC10E/100E151 s Available in 28-pin PLCC package FEATURES 6-BIT D REGISTER The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for the flip-flops. Data is clocked into the flip-flops on the rising edge of either CLK1 or CLK2 (or both). When both CLK1 and CLK2 are at a logic LOW, data enters the master and is transferred to the slave when either CLK1 or CLK2 (or both) go HIGH. The MR (Master Reset) signal operates asynchronously to make all Q outputs go to a logic LOW. DESCRIPTION SY10E151 SY100E151 BLOCK DIAGRAM Pin Function D0–D5 Data Inputs CLK1, CLK2 Clock Inputs MR Master Reset Q0–Q5 True Outputs Q0–Q5 Inverting Outputs VCCO VCC to Output PIN NAMES D R D R D R D R D R D R M R D0 CLK1 CLK2 D1 D2 D3 D4 D5 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 Rev.: G Amendment: /0 Issue Date: March 2006 |
Số phần tương tự - SY10E151 |
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Mô tả tương tự - SY10E151 |
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