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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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AT83C5103 bảng dữ liệu(PDF) 34 Page - ATMEL Corporation |
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AT83C5103 bảng dữ liệu(HTML) 34 Page - ATMEL Corporation |
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34 / 64 page  34 AT8xC5103 4134C–8051–09/04 Power Management Table 20. PCON Register PCON - Power Control Register (87h) Reset Value = XXX1 0000b Not bit addressable Idle Mode An instruction that sets PCON.0 indicates that it is the last instruction to be executed before going into the Idle Mode. In the Idle Mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator and all other registers maintain their data during Idle. The port pins hold the logical states they had at the time Idle was activated. There are two ways to terminate the Idle Mode. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating the Idle Mode. The interrupt will be serviced, and following RETI the next instruction to be executed will be the one fol- lowing the instruction that put the device into idle. The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred dur- ing normal operation or during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. The other way of terminating the Idle Mode is with a hardware reset. Since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset. 76 543 210 -- -- GF1 GF0 PD IDL Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3GF1 General-purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 2GF0 General-purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 1PD Power-Down Mode Bit Cleared by hardware when reset occurs. Set to enter Power-down Mode. 0IDL Idle Mode Bit Cleared by hardware when interrupt or reset occurs. Set to enter Idle Mode. |
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