AT89C51AC2 datasheet(37/121 Pages) ATMEL

37 / 121 page

A/T89C51AC2

4127G–8051–05/06

Overview of FM0

Operations

The CPU interfaces to the Flash memory through the FCON register and AUXR1

These registers are used to:

•

Map the memory spaces in the adressable space

•

Launch the programming of the memory spaces

•

Get the status of the Flash memory (busy/not busy)

Mapping of the Memory Space

By default, the user space is accessed by MOVC instruction for read only. The column

latches space is made accessible by setting the FPS bit in FCON register. Writing is

possible from 0000h to 7FFFh, address bits 6 to 0 are used to select an address within a

page while bits 14 to 7 are used to select the programming address of the page.

Setting FPS bit takes precedence on the EXTRAM bit in AUXR register.

The other memory spaces (user, extra row, hardware security) are made accessible in

the code segment by programming bits FMOD0 and FMOD1 in FCON register in accor-

dance with Table 24. A MOVC instruction is then used for reading these spaces.

Table 24. FM0 Blocks Select Bits

Launching Programming

FPL3:0 bits in FCON register are used to secure the launch of programming. A specific

sequence must be written in these bits to unlock the write protection and to launch the

programming. This sequence is 5xh followed by Axh. Table 25 summarizes the memory

spaces to program according to FMOD1:0 bits.

FMOD1

FMOD0

FM0 Adressable space

User (0000h-7FFFh)

Extra Row(FF80h-FFFFh)

Hardware Security Byte (0000h)

Reserved

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