AT26DF081A datasheet(25/40 Pages) ATMEL

25 / 40 page

3600F–DFLASH–03/07

AT26DF081A

10.1.6

WEL Bit

The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is

in the logical “0” state, the device will not accept any program, erase, Protect Sector, Unprotect

Sector, or Write Status Register commands. The WEL bit defaults to the logical “0” state after a

device power-up or reset. In addition, the WEL bit will be reset to the logical “0” state automati-

cally under the following conditions:

• Write Disable operation completes successfully

• Write Status Register operation completes successfully or aborts

• Protect Sector operation completes successfully or aborts

• Unprotect Sector operation completes successfully or aborts

• Byte/Page Program operation completes successfully or aborts

• Sequential Program Mode reaches highest unprotected memory location

• Sequential Program Mode reaches the end of the memory array

• Sequential Program Mode aborts

• Block Erase operation completes successfully or aborts

• Chip Erase operation completes successfully or aborts

• Hold condition aborts

If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation aborts

due to an incomplete or unrecognized opcode being clocked into the device before the CS pin is

deasserted. In order for the WEL bit to be reset when an operation aborts prematurely, the entire

opcode for a program, erase, Protect Sector, Unprotect Sector, or Write Status Register com-

mand must have been clocked into the device.

10.1.7

RDY/BSY Bit

The RDY/BSY bit is used to determine whether or not an internal operation, such as a program

or erase, is in progress. To poll the RDY/BSY bit to detect the completion of a program or erase

cycle, new Status Register data must be continually clocked out of the device until the state of

the RDY/BSY bit changes from a logical “1” to a logical “0”.

Figure 10-1. Read Status Register

SCK

MSB

00000101

410 11

21 22

15 16

13 14

23 24

OPCODE

MSB

DDDDDD

MSB

DDDDD

STATUS REGISTER DATA

HIGH-IMPEDANCE

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