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AT26F004 bảng dữ liệu(PDF) 21 Page - ATMEL Corporation |
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AT26F004 bảng dữ liệu(HTML) 21 Page - ATMEL Corporation |
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21 / 38 page ![]() 21 3588C–DFLASH–04/06 AT26F004 • Block Erase operation completes successfully or aborts • Chip Erase operation completes successfully or aborts If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation aborts due to an incomplete or unrecognized opcode being clocked into the device before the CS pin is deasserted. In order for the WEL bit to be reset when an operation aborts prematurely, the entire opcode for a program, erase, Protect Sector, Unprotect Sector, or Write Status Register com- mand must have been clocked into the device. 10.1.6 RDY/BSY Bit The RDY/BSY bit is used to determine whether or not an internal operation, such as a program or erase, is in progress. To poll the RDY/BSY bit to detect the completion of a program or erase cycle, new Status Register data must be continually clocked out of the device until the state of the RDY/BSY bit changes from a logical “1” to a logical “0”. Figure 10-1. Read Status Register SCK CS SI SO MSB 23 1 0 00000101 67 5 410 11 9 812 21 22 17 20 19 18 15 16 13 14 23 24 OPCODE MSB MSB DDDDDD D D D D MSB DDDDD D D D STATUS REGISTER DATA STATUS REGISTER DATA HIGH-IMPEDANCE |
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