®

LSN2 Series

Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters

www.cd4power.com

Figure 12. Wiring for Simultaneous Phasing

Figure 13. Self-Ramping Power Up

Figure 14. Proportional Phasing

Figure 15. Sequence/Track Simplified Equivalent Schematic

Figure 12 shows a basic Master (POL A) and Slave (POL B) connected so the

POL B ramps up identically to POL A as shown in timing diagram, Figure 8. RC

network R1 and C1 charge up at a rate set by the R1-C1 time constant, giving

B will stop rising. POL A then continues rising until it reaches 5V. R1 should be

significantly smaller than the internal bias current resistor from the Sequence

pin. Start with a 20k

Ω value. We assume that the critical phase is only on

power up therefore there is no provision for ramped power down.

Figure 13 shows a single POL and the same RC network. However, we have

POL, Q1 is biased on, shorting out the Sequence pin. When Q1’s gate is biased

off, R1 charges C1 and the POL’s output ramps up at the R1-C1 slew rate.

Note: Q1’s gate would typically be controlled from some external digital logic.

Guidelines for Sequence/Track Applications

[1]

Leave the converter’s On/Off Enable control (if installed) in the On setting.

Normally, you should just leave the On/Off pin open.

[2]

power on) before raising the Sequence input. Also, if you wish to have a

not simply shut off power.

[3]

[4]

Observe the Output slew rate relative to the Sequence input. A rough

guide is 2 Volts per millisecond maximum slew rate. If you exceed this

slew rate on the Sequence pin, the converter will simply ramp up at

it’s maximum output slew rate (and will not necessarily track the faster

Sequence input). The reason to carefully consider the slew rate limitation

is in case you want two different POL’s to precisely track each other.

If you wish to have a ramped power down (rather than a step down), add a

small resistor in series with Q1’s drain.

Figure 14 shows both a RC ramp on Master POL A and a proportional tracking

divider (R2 and R3) on POL B. We have also added an optional very small

noise filter cap at C2. Figure 14’s circuit corresponds roughly to Figure 9’s

timing for power up.