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AD8210YRZ bảng dữ liệu(PDF) 10 Page - Analog Devices

tên linh kiện AD8210YRZ
Giải thích chi tiết về linh kiện  High Voltage, Bidirectional Current Shunt Monitor
PDF  16 Pages
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nhà sản xuất  AD [Analog Devices]
Trang chủ  http://www.analog.com
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AD8210YRZ bảng dữ liệu(HTML) 10 Page - Analog Devices

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AD8210
Rev. 0 | Page 10 of 16
THEORY OF OPERATION
In typical applications, the AD8210 amplifies a small differential
input voltage generated by the load current flowing through a
shunt resistor. The AD8210 rejects high common-mode voltages
(up to 65 V) and provides a ground referenced buffered output
that interfaces with an analog-to-digital converter. Figure 26
shows a simplified schematic of the AD8210.
The AD8210 is comprised of two main blocks, a differential
amplifier and an instrumentation amplifier. A load current
flowing through the external shunt resistor produces a voltage
at the input terminals of the AD8210. The input terminals are
connected to the differential amplifier (A1) by Resistor R1 and
Resistor R2. A1 nulls the voltage appearing across its own input
terminals by adjusting the current through R1 and R2 with
Transistor Q1 and Transistor Q2. When the input signal to the
AD8210 is 0 V, the currents in R1 and R2 are equal. When the
differential signal is nonzero, the current increases through one
of the resistors and decreases in the other. The current
difference is proportional to the size and polarity of the input
signal.
The differential currents through Q1 and Q2 are converted into
a differential voltage by R3 and R4. A2 is configured as an
instrumentation amplifier. The differential voltage is converted
into a single-ended output voltage by A2. The gain is internally
set with precision trimmed, thin film resistors to 20 V/V.
The output reference voltage is easily adjusted by the VREF1 pin
and VREF2 pin. In a typical configuration, VREF1 is connected to
VCC while VREF2 is connected to GND. In this case, the output is
centered at VCC/2 when the input signal is 0 V.
ISHUNT
RSHUNT
AD8210
VOUT =(ISHUNT ×RSHUNT)× 20
A2
R1
R2
VS
VREF1
VREF2
GND
A1
R3
R4
Q1
Q2
Figure 26. Simplified Schematic



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