M45PE80 datasheet(36/47 Pages) STMICROELECTRONICS

36 / 47 page

DC and AC parameters

M45PE80

36/47

Table 12.

AC characteristics (25 MHz operation)

Test conditions specified in Table 8 and Table 9

Symbol

Alt.

Parameter

Min.

Typ.

Max.

Unit

Clock Frequency for the following

instructions: FAST_READ, PW, PP, PE,

SE, DP, RDP, WREN, WRDI, RDSR

D.C.

MHz

Clock Frequency for READ instructions

D.C.

MHz

tCH

(1)

tCH + tCL must be greater than or equal to 1/ fC

tCLH Clock High Time

tCL

(1)

tCLL Clock Low Time

Clock Slew Rate(2) (peak to peak)

0.03

V/ns

tSLCH

tCSS S Active Setup Time (relative to C)

tCHSL

S Not Active Hold Time (relative to C)

tDVCH

tDSU Data In Setup Time

tCHDX

tDH

Data In Hold Time

tCHSH

S Active Hold Time (relative to C)

tSHCH

S Not Active Setup Time (relative to C)

tSHSL

tCSH S Deselect Time

200

tSHQZ

(2)

Value guaranteed by characterization, not 100% tested in production.

tDIS

Output Disable Time

tCLQV

Clock Low to Output Valid

tCLQX

tHO

Output Hold Time

tSHRH

Chip should have been deselected

before Reset is de-asserted

tWHSL

Write Protect Setup Time

tSHWL

Write Protect Hold Time

100

tDP

(2)

S to Deep Power-down

µs

tRDP

(2)

S High to Standby Mode

µs

tPW

(3)

When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one

sequence including all the bytes versus several sequences of only a few bytes. (1

≤n ≤256)

Page Write Cycle Time (256 bytes)

Page Write Cycle Time (n bytes)

10.2+

n*0.8/256

tPP

(3)

Page Program Cycle Time (256 bytes)

1.2

5ms

Page Program Cycle Time (n bytes)

0.4+

n*0.8/256

tPE

Page Erase Cycle Time

tSE

Sector Erase Cycle Time

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