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(N+1). In this case, data in both the ADC output buffer and the FIFO buffer are updated at the same time (that

is, both buffers now hold the same conversion data N+1).

• If conversion data (N) stored in the FIFO buffer has not yet been read by the host when new conversion

data (N+1) become available, then the FIFO buffer is not updated and still holds the previous conversion

data (N), while the ADC output buffer now holds the new conversion data (N+1). In this case, data content is

different between the ADC output buffer (N+1) and the FIFO buffer (N). After the host reads conversion data

N from the FIFO buffer, the FIFO buffer is updated with the conversion data N+1. The host can then retrieve

conversion data N+1.

• A special scenario exists if conversion data (N) stored in the FIFO buffer has not been read by the host, but

two new conversion data already became available in the meantime (that is, the ADC output buffer is updated

with conversion data N+2). In this case, the FIFO buffer is updated with conversion result N+2 at the same

time the ADC output buffer is updated with conversion result N+2 (that is, both buffers now hold the same

conversion data N+2). That means, conversion data N and N+1 are lost and cannot be retrieved by the host

anymore.

Table 8-12 summarizes the ADC output buffer and FIFO buffer operation when new conversion data (N+1) are

available.

Table 8-12. New Conversion Data Available: Operation of the ADC Output Buffer and FIFO Buffer

SPI HISTORY

NEW CONVERSION

DATA AVAILABLE AT

TIME t = tS

ADC OUTPUT BUFFER

CONTENT (t < tS)

FIFO BUFFER

CONTENT (t < tS)

ADC OUTPUT BUFFER

CONTENT (t > tS)

FIFO BUFFER

CONTENT (t > tS)

FIFO data N has been

read by the host

N+1

FIFO data N has not yet

been read by the host

N+1

FIFO data N has not yet

been read by the host

N+2

N+1

N+2

The following three examples illustrate the behavior of the ADC output and FIFO buffer using a simplified

notation to indicate which conversion data is stored in each buffer: [number of sample in the ADC output buffer |

number of sample in the FIFO buffer].

Example 1: Host reads conversion results as soon as the results become available

• When the first conversion (result 1) completes, this result is placed both in the ADC output buffer and the

FIFO buffer [1 | 1].

• If the host reads conversion result 1 immediately after the conversion completes, the content of the buffers

stays at [1 | 1]. The host can read conversion result 1 from the FIFO buffer multiple times if needed before

conversion result 2 completes.

• When conversion result 2 completes, the result is again placed into both the ADC output buffer and the FIFO

buffer [2 | 2].

• If the host reads the result before the third conversion completes, result 2 is read out and the buffers stay at

[2 | 2].

Example 2: Host misses reading one conversion result

• When the first conversion (result 1) completes, the result is placed both in the ADC output buffer and the

FIFO buffer [1 | 1].

• If the host misses reading result 1 from the FIFO buffer before the second conversion completes, then the

ADC output buffer holds result 2, and the FIFO buffer still holds result 1 [2 | 1].

• If the host now reads data before the third conversion completes, result 1 is read. The content of the buffers

then updates to [2 | 2].

• Another conversion data read request by the host shifts out result 2 on DOUT. The buffers stay at [2 | 2].

• Now when the third conversion completes, both buffers update with result 3 [3 | 3].

Example 3: Host misses reading two consecutive conversion results

• When the first conversion (result 1) completes, the result is placed both in the ADC output buffer and the

FIFO buffer [1 | 1].

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AMC131M02

SBASA56 – SEPTEMBER 2023

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