ADC32RF52 datasheet(48/108 Pages) TI

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7.3.6.2 JESD204B Frame Assembly

The JESD204B standard defines the following parameters:

• L: number of lanes per link

• M: number of converters per device

• F: number of octets per frame clock period

• S: number of samples per frame

7.3.6.3 JESD204B Frame Assembly in Bypass Mode

Table 7-31 lists the available JESD204B formats and corresponding valid sampling rate ranges for the

ADC32RF5x. The sampling rates are limited by the minimum and maximum SERDES line rate as well as ADC

sampling clock frequencies. The JESD204B frame assembly for the different lanes is shown in Table 7-32.

When internal digital averaging is used, the output resolution is automatically adjusted from 14-bit to 16-bit to

avoid quantization noise limitation.

Table 7-31. JESD Mode Options: Bypass Mode

DECIMATION

SETTING D

(complex)

OUTPUT

RESOLUTION

(Bits)

MIN FS

(Gsps)

MAX FS

(Gsps)

RATIO

[fSERDES/FS]

Bypass

12(1)

0.5

1.5

14/16(2)

0.5

1.5

0.5

1.5

(1) In this output mode, two LSBs are truncated to a 12-bit output.

(2) When using digital averaging the output resolution changes to 16-bit.

Table 7-32. JESD Sample Frame Assembly: Bypass Mode

OUTPUT

LANE

LMFS = 82820

LMFS = 8224

LMFS = 4222

DOUT0

A0[11:4]

A0[3:0],

A1[11:8]

A1[7:0]

A2[11:4]

A2[3:0],

A3[11:8]

A3[7:0]

A4[11:4]

A4[3:0],

0000

A0[13:6]

A0[5:0],

A0[13:6]

A0[5:0],

DOUT1

A5[11:4]

A5[3:0],

A6[11:8]

A6[7:0]

A7[11:4]

A7[3:0],

A8[11:8]

A8[7:0]

A9[11:4]

A9[3:0],

0000

A1[13:6]

A1[5:0],

A1[13:6]

A1[5:0],

DOUT2 A10[11:4]

A10[3:0],

A11[11:8]

A11[7:0] A12[11:4]

A12[3:0],

A13[11:8]

A13[7:0] A14[11:4]

A14[3:0],

0000

A2[13:6]

A2[5:0],

B0[13:6]

B0[5:0],

DOUT3 A15[11:4]

A15[3:0],

A16[11:8]

A16[7:0] A17[11:4]

A17[3:0],

A18[11:8]

A18[7:0] A19[11:4]

A19[3:0],

0000

A3[13:6]

A3[5:0],

B1[13:6]

B1[5:0],

DOUT4

B0[11:4]

B0[3:0],

B1[11:8]

B1[7:0]

B2[11:4]

B2[3:0],

B3[11:8]

B3[7:0]

B4[11:4]

B4[3:0],

0000

B0[13:6]

B0[5:0],

DOUT5

B5[11:4]

B5[3:0],

B6[11:8]

B6[7:0]

B7[11:4]

B7[3:0],

B8[11:8]

B8[7:0]

B9[11:4]

B9[3:0],

0000

B1[13:6]

B1[5:0],

DOUT6 B10[11:4]

B10[3:0],

B11[11:8]

B11[7:0] B12[11:4]

B12[3:0],

B13[11:8]

B13[7:0] B14[11:4]

B14[3:0],

0000

B2[13:6]

B2[5:0],

DOUT7 B15[11:4]

B15[3:0],

B16[11:8]

B16[7:0] B17[11:4]

B17[3:0],

B18[11:8]

B18[7:0] B19[11:4]

B19[3:0],

0000

B3[13:6]

B3[5:0],

ADC32RF52

SBASAI6 – SEPTEMBER 2023

www.ti.com

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