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AT89C5131A-RDTIM bảng dữ liệu(PDF) 15 Page - ATMEL Corporation

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AT89C5130A/31A-M
4337G–USB–11/06
Figure 8.
Crystal Connection
PLL
PLL Description
The AT89C5130A/31A-M PLL is used to generate internal high frequency clock (the
USB Clock) synchronized with an external low-frequency (the Peripheral Clock). The
PLL clock is used to generate the USB interface clock. Figure 9 shows the internal
structure of the PLL.
The PFLD block is the Phase Frequency Comparator and Lock Detector. This block
makes the comparison between the reference clock coming from the N divider and the
reverse clock coming from the R divider and generates some pulses on the Up or Down
signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON
register is used to enable the clock generation. When the PLL is locked, the bit PLOCK
in PLLCON register (see Figure 9) is set.
The CHP block is the Charge Pump that generates the voltage reference for the VCO by
injecting or extracting charges from the external filter connected on PLLF pin (see
Figure 10). Value of the filter components are detailed in the Section “DC
Characteristics”.
The VCO block is the Voltage Controlled Oscillator controlled by the voltage VREF pro-
duced by the charge pump. It generates a square wave signal: the PLL clock.
Figure 9.
PLL Block Diagram and Symbol
Figure 10.
PLL Filter Connection
The typical values are: R = 100
Ω, C1 = 10 nf, C2 = 2.2 nF.
VSS
X1
X2
Q
C1
C2
PLLEN
PLLCON.1
N3:0
N divider
R divider
VCO
USB Clock
USBclk
OSC
clk
R 1
+
()
×
N1
+
-----------------------------------------------
=
OSC
CLOCK
PFLD
PLOCK
PLLCON.0
PLLF
CHP
Vref
Up
Down
R3:0
USB
CLOCK
USB Clock Symbol
VSS
PLLF
R
C1
C2
VSS



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