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WM8983GEFL/RV bảng dữ liệu(PDF) 85 Page - Wolfson Microelectronics plc |
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WM8983GEFL/RV bảng dữ liệu(HTML) 85 Page - Wolfson Microelectronics plc |
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85 / 123 page ![]() Production Data WM8983 w PD Rev 4.0 November 2006 85 AUDIO SAMPLE RATES The WM8983 filter characteristics for the ADCs and the DACs are set using the SR register bits; these bits do not change the rate of the audio interface output clocks in Master mode. The cut-offs for the digital filters and the ALC attack/decay times stated are determined using these values and assume a 256fs master clock rate. If a sample rate is required which is not explicitly supported by the SR register settings, then the closest SR value to that sample rate should be chosen, the filter characteristics and the ALC attack, decay and hold times will scale appropriately. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R7 Additional Control 3:1 SR 000 Approximate sample rate (configures the coefficients for the internal digital filters): 000 = 48kHz 001 = 32kHz 010 = 24kHz 011 = 16kHz 100 = 12kHz 101 = 8kHz 110-111 = reserved Table 57 Sample Rate Control MASTER CLOCK AND PHASE LOCKED LOOP (PLL) The WM8983 has an on-chip phase-locked loop (PLL) circuit that can be used to: Generate master clocks for the WM8983 audio functions from another external clock, e.g. in telecoms applications. Generate and output (on pin CSB/GPIO1) a clock for another part of the system that is derived from an existing audio master clock. Figure 49 shows the PLL and internal clocking on the WM8983. The PLL can be enabled or disabled by the PLLEN register bit. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1 Power management 1 5 PLLEN 0 PLL enable 0 = PLL off 1 = PLL on Table 58 PLLEN Control Bit |
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