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WM8785GEDS/V bảng dữ liệu(PDF) 24 Page - Wolfson Microelectronics plc |
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WM8785GEDS/V bảng dữ liệu(HTML) 24 Page - Wolfson Microelectronics plc |
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24 / 31 page ![]() WM8785 Production Data w PD Rev 4.1 December 2006 24 Figure 29 WM8785 in Time Division Multiplexing Left Justified Mode Up to 4 devices (8 channels) can be supported, which would require 256 BCLKs per sample. (whereas 128 BCLKs will allow only 2 devices, or 4 channels). The table below shows the range of BCLK frequencies required. BCLK RATE DEVICES THAT CAN BE SUPPORTED OVER-SAMPLE RATIOS SUPPORTED (SET BY OSR) 64 fs 128 fs 192 fs 1 1, 2 1, 2 Single/dual/quad rates all supported 256 fs 1, 2, 3, 4 Single rate only supported Table 6 Range of BCLK Frequencies Required Note: MCLK frequency must always be greater or equal to BCLK frequency To avoid bus contention all chips on the TDM should be programmed before DOUT is released after power up (DOUT is held at vss for 32 samples after power-up). Alternatively SDODIS should be set while devices are programmed (to tri-state DOUT). |
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