M50FW040 datasheet(18/53 Pages) STMICROELECTRONICS

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Bus operations

M50FW040

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3.1.3

Bus Abort

The Bus Abort operation can be used to immediately abort the current bus operation. A Bus

Abort occurs when FWH4 is driven Low, VIL, during the bus operation; the memory will tri-

state the Input/Output Communication pins, FWH0-FWH3.

Note that, during a Bus Write operation, the Command Interface starts executing the

command as soon as the data is fully received; a Bus Abort during the final TAR cycles is

not guaranteed to abort the command; the bus, however, will be released immediately.

3.1.4

Standby

When FWH4 is High, VIH, the memory is put into Standby mode where FWH0-FWH3 are

put into a high-impedance state and the Supply Current is reduced to the Standby level,

ICC1.

3.1.5

Reset

During Reset mode all internal circuits are switched off, the memory is deselected and the

outputs are put in high-impedance. The memory is in Reset mode when Interface Reset, RP,

or CPU Reset, INIT, is Low, VIL. RP or INIT must be held Low, VIL, for tPLPH. The memory

resets to Read mode upon return from Reset mode and the Lock Registers return to their

default states regardless of their state before Reset, see Table 10 If RP or INIT goes Low,

VIL, during a Program or Erase operation, the operation is aborted and the memory cells

affected no longer contain valid data; the memory can take up to tPLRH to abort a Program

or Erase operation.

3.1.6

Block Protection

Block Protection can be forced using the signals Top Block Lock, TBL, and Write Protect,

WP, regardless of the state of the Lock Registers.

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