CAT25C256VT2 datasheet(8/12 Pages) CATALYST

8 / 12 page

CAT25C128/256

Document No. 1018, Rev. I

properly set. Also, for a successful write operation the

address of the memory location(s) to be programmed

must be outside the protected address field location

selected by the block protection level.

Byte Write

Once the device is in a Write Enable state, the user may

proceed with a write sequence by setting the

CS low,

issuing a write instruction via the SI line, followed by the

16-bit address (the three Most Significant Bits are don’t

care for 25C256 and four most significant bits are don't

care for 25C128), and then the data to be written.

Programming will start after the

CS is brought high. Figure

6 illustrates byte write sequence.

During an internal write cycle, all commands will be

ignored except the RDSR (Read Status Register)

instruction.

To read the status register, RDSR instruction should be

sent. The contents of the status register are shifted out

on the SO line. The status register may be read at any

time even during a write cycle. Read sequece is illus-

trated in Figure 4. Reading status register is illustrated in

Figure 5.

WRITE Sequence

The CAT25C128/256 powers up in a Write Disable

state. Prior to any write instructions, the WREN instruc-

tion must be sent to CAT25C128/256. The device goes

into Write enable state by pulling the

CS low and then

clocking the WREN instruction into CAT25C128/256.

The

CS must be brought high after the WREN instruction

to enable writes to the device. If the write operation is

initiated immediately after the WREN instruction without

CS being brought high, the data will not be written to the

array because the write enable latch will not have been

0000001

BYTE ADDRESS*

0123456789

*Please check the instruction set table for address

OPCODE

DATA OUT

MSB

HIGH IMPEDANCE

Note: Dashed Line= mode (1, 1) — ———

Figure 4. Read Instruction Timing

Figure 5. RDSR Timing

345

911

SCK

DATA OUT

MSB

HIGH IMPEDANCE

OPCODE

Note: Dashed Line= mode (1, 1) — ———

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