5CEBA2F13C6SC datasheet(25/37 Pages) INTEL

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External Memory Performance

Table 20.

External Memory Interface Performance in Cyclone V Devices

The maximum and minimum operating frequencies depend on the memory interface standards and the

supported delay-locked loop (DLL) frequency listed in the device datasheet.

Interface

Voltage

(V)

Maximum Frequency (MHz)

Minimum Frequency

(MHz)

Hard Controller

Soft Controller

DDR3 SDRAM

1.5

400

303

1.35

400

303

DDR2 SDRAM

1.8

400

300

167

LPDDR2 SDRAM

1.2

333

300

167

Related Information

External Memory Interface Spec Estimator

For the latest information and to estimate the external memory system

performance specification, use Intel's External Memory Interface Spec Estimator

tool.

HPS External Memory Performance

Table 21.

HPS External Memory Interface Performance

The hard processor system (HPS) is available in Cyclone V SoC devices only.

Interface

Voltage (V)

HPS Hard Controller (MHz)

DDR3 SDRAM

1.5

400

1.35

400

DDR2 SDRAM

1.8

400

LPDDR2 SDRAM

1.2

333

Related Information

External Memory Interface Spec Estimator

For the latest information and to estimate the external memory system

performance specification, use Intel's External Memory Interface Spec Estimator

tool.

Low-Power Serial Transceivers

Cyclone V devices deliver the industry’s lowest power 6.144 Gbps transceivers at an

estimated 88 mW maximum power consumption per channel. Cyclone V transceivers

are designed to be compliant with a wide range of protocols and data rates.

Transceiver Channels

The transceivers are positioned on the left outer edge of the device. The transceiver

channels consist of the physical medium attachment (PMA), physical coding sublayer

(PCS), and clock networks.

Cyclone V Device Overview

683694 | 2018.05.07

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Cyclone V Device Overview

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