CAT25010 datasheet(9/18 Pages) CATALYST

9 / 18 page

CAT25010, CAT25020, CAT25040

Doc. No. 1006, Rev. S

Characteristics subject to change without notice

Figure 9.

HOLD

HOLD Timing

Figure 8. Page Write Instruction Timing

Note: Dashed Line= mode (1, 1) – ––––

*X=0 for 25010, 25020 ; X=A8 for 25040

Note: Dashed Line= mode (1, 1) – ––––

SCK

HOLD

tCD

tHD

tCD

tLZ

tHZ

HIGH IMPEDANCE

SCK

BYTE ADDRESS

Data

Byte 1

012345678

15 16-23

24-31

Data

Byte 2

Data

Byte 3

Data Byte N

OPCODE

7..1

16+(N-1)x8-1..16+(N-1)x8 16+Nx8-1

DATA IN

HIGH IMPEDANCE

Figure 10.

WP Timing

SCK

tWPS

tWPH

Note: Dashed Line= mode (1, 1) – ––––

must be set high after the proper number of clock cycles

to start an internal write cycle. Access to the array

during an internal write cycle is ignored and program-

ming is continued. On power up, SO is in a high

impedance. If an invalid opcode is received, no data will

be shifted into the CAT25010/20/40, and the serial

output pin (SO) will remain in a high impedance state

until the falling edge of

CS is detected again.

DESIGN CONSIDERATIONS

The CAT25010/20/40 powers up in a write disable state

and in a low power standby mode. A WREN instruction

must be issued to perform any writes to the device after

power up. After power up,

CS must be brought low to

enter a ready state and receive an instruction. After a

successful byte/page write or status register write, the

CAT25010/20/40 goes into a write disable mode.

CAT25010 bảng dữ liệu(PDF) 9 Page - Catalyst Semiconductor

CAT25010 bảng dữ liệu(HTML) 9 Page - Catalyst Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

bảng dữ liệu tải về

Link URL