SST25VF040B datasheet(4/31 Pages) MICROCHIP

4 / 31 page

 2005-2020 Microchip Technology Inc.

DS20005051F-page 4

SST25VF040B

2.0

PIN DESCRIPTION

FIGURE 2-1:

PIN ASSIGNMENTS

TABLE 2-1:

PIN DESCRIPTION

Symbol

Pin Name

Functions

CE#

Chip Enable

The device is enabled by a high to low transition on CE#. CE# must remain low for the

duration of any command sequence.

Serial Data Output To transfer data serially out of the device.

Data is shifted out on the falling edge of the serial clock.

Outputs Flash busy status during AAI Programming when reconfigured as RY/BY#

pin. See Section 5.5 “End of Write Detection” for details.

WP#

Write-Protect

The Write-Protect (WP#) pin is used to enable/disable BPL bit in the STATUS register.

VSS

Ground

VDD

Power Supply

To provide power supply voltage:2.7V-3.6V for SST25VF040B.

HOLD#

Hold

To temporarily stop serial communication with SPI Flash memory without resetting the

device.

SCK

Serial Clock

To provide the timing of the serial interface.

Commands, addresses, or input data are latched on the rising edge of the clock input,

while output data is shifted out on the falling edge of the clock input.

Serial Data Input

To transfer commands, addresses, or data serially into the device.

Inputs are latched on the rising edge of the serial clock.

Pin Assignment for 8-Lead SOIC

Pin Assignment for 8-Contact WSON

Top View

CE#

WP#

HOLD#

SCK

CE#

WP#

VSS

VDD

HOLD#

SCK

Top View

SST25VF040B bảng dữ liệu(PDF) 4 Page - Microchip Technology

SST25VF040B bảng dữ liệu(HTML) 4 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

bảng dữ liệu tải về

Link URL