PDSP1601 datasheet(2/18 Pages) ZARLINK

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PDSP16116/A/MC

Signal

XR15:0

XI15:0

YR15:0

YI15:0

PR15:0

PI15:0

CLK

CEX

CEY

CONX

CONY

ROUND

MBFP

SOBFP

EOPSS

AR15:13

AI15:13

WTA1:0

WTB1:0

WTOUT1:0

SFTA1:0

SFTR2:0

GWR4:0

OSEL1:0

OER, OEI

VDD

GND

The PDSP16116 has a number of features tailored for

System applications.

-1 x -1 Trap

In multiply operations utilising Twos Complement

Fractional notation, the -1 x -1 operation forms an invalid result

as +1 is not representable in the fractional number range. The

PDSP16116/A eliminates this problem by trapping the

-1 x -1 operation and forcing the Multiplier result to become the

most positive representable number.

Complex Conjugation

Many algorithms utilising complex arithmetic require

conjugation of complex data stream.

This operation has

traditionally required an adiditional ALU to multiply the

imaginary component by -1. The PDSP16116 eliminates the

requirement for the extra ALU by offering on chip complex

conjugation of either of the two incoming complex data words

with no loss in throughput.

Easy Interfacing

As with all PDSP family members the PDSP16116 has

registered I/O for data and control.

Data inputs have

independent clock enables and data outputs have

independent three state output enables.

Type

INPUT

OUTPUT

INPUT

OUTPUT

INPUT

POWER

Description

16 bit input for real x data

16 bit input for imag x data

16 bit input for reaal y data

16 bit input for imag y data

16 bit output for real p data

16 bit output for img p data

Clock, new data is loaded on rising edge of CLK

Clock, enable X-port input register

Clock, enable Y-port input register

Conjugate X data

Conjugate Y data

Rounds the real & imag results

Mode select (BFP/Normal)

Start of BFP operations **

End of pass **

3 MSB's from real part of A-word **

3 MSB's from imag part of A-word **

Word tag from A-word

Word tag from B-word / shift control *

Word tag output **

Shift control for A-word / overflow flag *

Shift control for accumulator resul **

Global weighting register contents **

Selects the desired output configuration

Output enables

+5V Supply

All supply pins

0V Supply

must be connected

Normal mode Configuration

Tie Low

Indicates pin performs different functions in BFP / Normal modes.

** Indicates pin is used only in BFP mode

Table.1 Signal Descriptions

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