AT80C51RA2-3CSCL datasheet(49/85 Pages) IRF

49 / 85 page

4188E–8051–08/06

AT/TS8xC51Rx2

Power-Off Flag

The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start”

reset.

A cold start reset is the one induced by V

CC switch-on. A warm start reset occurs while VCC is still

applied to the device and could be generated for example by an exit from power-down.

The power-off flag (POF) is located in PCON register (See Table 7-1). POF is set by hardware

when VCC rises from 0 to its nominal voltage. The POF can be set or cleared by software allow-

ing the user to determine the type of reset.

The POF value is only relevant with a Vcc range from 4.5V to 5.5V. For lower Vcc value, reading

POF bit will return indeterminate value.

Table 7-1.

PCON Register

PCON - Power Control Register (87h)

Reset Value = 00X1 0000b

Not bit addressable

SMOD1

SMOD0

POF

GF1

GF0

IDL

Bit

Number

Bit

Mnemonic

Description

7SMOD1

Serial port Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.

6SMOD0

Serial port Mode bit 0

Clear to select SM0 bit in SCON register.

Set to to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

4POF

Power-Off Flag

Clear to recognize next reset type.

Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by

software.

3GF1

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

2GF0

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

1PD

Power-Down mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

0IDL

Idle mode bit

Clear by hardware when interrupt or reset occurs.

Set to enter idle mode.

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