CONFIDENTIAL INFORMATION Rev. 1.2

May 4, 2020

SABRE9006ADatasheet

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-

8800 • Fax (408) 643-8801

16

Register #27-24: Master Trim

(default = 32’h7FFFFFFF)

This is a 32 bit value that sets the 0dB level for all volume controls. This is a signed number, so it should never exceed

32'h7fffffff (which is 231 - 1). Register 27contains the MSBs, Register 24 contains the LSBs.

Register #64: DAC Status

[7:5]: Chip_id

Returns

3’d4 (SABRE9006A)

[3:2]: Reserved

[1]: Automute_status

1'b1 => Auto-mute condition is active.

1'b0 => Auto-mute condition is inactive.

[0]: Lock_status

1'b1 => The Jitter Eliminator is locked to an incoming signal.

1'b0 => The Jitter Eliminator is not locked to an incoming signal.

Register #69-66: DPLL_NUM

32-bit, Read-Only Register. Register 69 contains the MSBs, Register 66 contains the LSBs

This is a read-only 32-bit value that can be used to calculate the sample rate. The sample rate (Fin) can be calculated using:

Fin = (DPLL_NUM x FMCLK) / 232.

Register #93-70

Register 93 contains the MSBs, Register 70 contains the LSBs. Format is [191:0]

These registers allow read back of the SPDIF channel status. The status definition is different for the consumer configuration

and professional configuration. Please refer to the following two tables for details.