ES9826 datasheet(36/88 Pages) ESS

36 / 88 page

ES9826 Datasheet

VERSION 0.1.2

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • WWW.ESSTECH.COM

Analog Phase Locked Loop (APLL)

DATA_CLK

REG 1V8

NFB

REG 1V2

FOUT

ACLK

Figure 12 - Functional Block Diagram of ES9826 APLL

The ES9826 has a built in Analog PLL (APLL) for generating frequencies that are unavailable externally. For the application

note on the APLL, please ask your FAE or distributor.

For calculation of the PLL frequency output, use the following formulas:

Where:

a. FBDIV is a 24-bit number

b. PLL frequency range requirements:

a. Fref requirement: 2.5MHz < Fref < 12 MHz

b. Fvco requirement: 90MHz < Fvco < 110MHz

c. Fout requirement: 22.5792/24.576MHz & 45.1584/49.152Mhz

c. Ni = input divider

• Accessible from Reg 202-200[9:1], PLL_CLK_IN_DIV

d. No = output divider

• Accessible from Reg 202-200[13:10], PLL_CLK_OUT_DIV

e. Nfb = feedback divider

• Accessible from Reg 199-197[23:0], PLL_CLK_FB_DIV

Programmable Microphone Regulator (MICBIAS)

ES9826 integrates a low noise programmable regulator intended to power or bias external microphones. MICBIAS is

nominally 2.8V but can be programmed from 1.4-2.8V.

In hardware mode, MICBIAS is disabled.

In software mode, MICBIAS can be enabled by setting Register 78[3] - MB PDB to 1’b1. To program MICBIAS to other

voltages, first set Register 78[6] - MB VR BYPASS and controlled by Register 78 [2:0] - MB VR SET.

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