ES9820Q datasheet(24/117 Pages) ESS

24 / 117 page

CONFIDENTIAL ADVANCE INFORMATION 0.3

ES9820 Product Datasheet

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

The following list shows the various clocks of the ES9820 and the associated registers for configuration.

Analog ADC Clock

ADC clock must be maintained to be between 22.5792MHz & 24.576MHz

•

Reg 194[0] (SEL_CLK_DIV)

•

Reg 193[2:1] (SEL_SYSCLK_IN)

•

Reg 193[0] (EN_ANA_CLKIN)

IADC Clock (Digital Input ADC Clock)

Should be set to the same clock frequency as the analog ADC clock, sampling Analog ADC

•

Reg 3[2:0] (SELECT_IADC_NUM)

Set this so it matches Analog ADC clock of 22.5792 or 24.576MHz

•

Reg 1

Dependent on channels required

•

Reg 193[2:1] (SEL_SYSCLK_IN)

•

Reg 193[0] (EN_ANA_CLKIN)

ADC Decimation Path Clock

•

Reg 2[4:0] (SELECT_ADC_NUM)

•

Reg 1

Dependent on channels required

•

Reg 9[6:0]

•

Reg 193[2:1] (SEL_SYSCLK_IN)

•

Reg 193[0] (EN_ANA_CLKIN)

Master BCK & WS

•

Reg 8

•

Reg 7[7:5] MASTER_WS_SCALE

•

Reg 9[6:0] SELECT_I2S_TDM_NUM

•

Reg 193[2:1] (SEL_SYSCLK_IN)

•

Reg 193[0] (EN_ANA_CLKIN)

TDM Clock

•

Reg 10[0] (ENABLE_TDM_CLK)

S/PDIF Clock

•

Reg 5[2] (ENABLE_SPDIF_CLK)

ASP1 Clock

•

Reg 35[0] (ENABLE_ASP1_CLK)

•

Reg 35[5:1] (SELECT_ASP1_NUM)

•

Reg 1

Dependent on channels required

•

Reg 193[2:1] (SEL_SYSCLK_IN)

•

Reg 193[0] (EN_ANA_CLKIN)

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