MPQ4480 – 36V, 6A, SYNC STEP-DOWN CONVERTER FOR AEC1-Q100 QUALIFIED

MPQ4480 Rev. 1.0

www.MonolithicPower.com

19

7/2/2019

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For

an

electrolytic

capacitor,

the

ESR

dominates the impedance at the switching

frequency. For simplification, the output ripple

can be estimated with Equation (11):



 









OUT

OUT

OUT

ESR

IN

SW

1

VV

∆V1

R

fL

V

(11)

For polymer capacitor designs, the ESR of

output capacitor should be less than 50mΩ.

PCB Layout Guidelines (8)

Proper PCB layout is critical for efficient

operation and thermal dissipation. For best

results, refer to Figure 8 and follow the

guidelines below:

1. Place the high-current paths (GND, IN, and

SW) very close to the device with short,

direct, and wide traces.

2. Use a large copper plane for PGND. Add

multiple vias to improve thermal dissipation.

3. Connect AGND to PGND.

4. Ensure that FB is far from SW to avoid

noise.

5. To improve EMI performance, place two

ceramic input decoupling capacitors as

close as possible to IN and PGND.

6. Place the VCC decoupling capacitor as

close as possible to VCC.

Note:

8) The recommended layout is based on the Typical Application

Circuits on page 19.

Top Layer

Middle Layer 1

Middle Layer 2

Bottom Layer

Figure 8: Recommend Layout

VIN

PGND

USB_GND

PGND

PGND

SW

VOUT

PGND

USB_GND

PGND

PGND