MP6605C

– 4-CHANNEL LOW-SIDE DRIVER WITH I2C INTERFACE

MP6605C Rev. 1.0

MonolithicPower.com

6

7/11/2022

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I2C TIMING CHARACTERISTICS (6)

VIN = 24V, TA = 25°C, unless otherwise noted.

Parameter

Symbol

Condition

Min

Typ

Max

Units

SCL clock frequency

fSCL

10

500

kHz

Bus free time

tBUF

Between stop and start condition

0.5

μs

Holding time after repeated

start command

tHD_STA

After this period, the first clock is

generated

0.26

μs

Repeated start command set-

up time

tSU_STA

0.26

μs

Stop condition set-up time

tSU_STO

0.26

μs

Data hold time

tHD_DAT

0

ns

Data set-up time

tSU_DAT

50

ns

Clock low time

tLOW

0.5

μs

Clock high time

tHIGH

0.26

50

μs

Clock/data falling time

tF

120

ns

Clock/data rising time

tR

120

ns

Note:

6) Not subject to production testing. Specified by design.

I2C TIMING DIAGRAM

SDA

SCL

S

S = Start Command

Sr = Repeated Start Command

P = Stop Command

tLOW

tR

tHD_DAT

tSU_DAT

tHIGH

tSU_STA

tF

tF

Sr

tHD_STA

tR

tSU_STO

P

S

tBUF