ZSSC1750 datasheet(39/117 Pages) RENESAS

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ZSSC1750 / ZSSC1751 Datasheet

April 20, 2016

3.3.4.5

Table 3.8

Name

Address

Bits

Default

Access

Description

disVddpRst

B9HEX

[0]

0BIN

When set to 1, VddpReset does not generate a

MCU_RSTN signal to reset the external

microcontroller.

disStoOut

[1]

0BIN

When set to 1, the output driver of the STO pin is

disabled.

Unused

[7:2] 000000BIN

Unused; always write as 0.

3.4

SBC Watchdog Timer (WD_TIMER Block)

The SBC contains a configurable watchdog timer (down counter) for the ZSSC1750/51 when it is running using

the clock from the low-power oscillator. It is used to recover from an invalid software or hardware state. To avoid

a reset of the system, the watchdog must be periodically serviced. The only part of the system that will not be

reset by the watchdog reset is the watchdog itself and its configuration registers.

Figure 3.2

Structure of the Watchdog Timer

Configurable

Prescaler

1 : 1

1 : 125

1 : 1250

1 : 12500

lpClk

(125 kHz)

16-Bit Down

Counter

wdogPrescaleCfg

(register file)

set

wdogCnt (register file)

wdIrq (IRQ ctrl)

wdogIrqFuncEna (register file)

wdRst (RstCtrl)

set

By default, the watchdog timer is active starting with a counter value of FFFFHEX and a prescaler of 125. This is

done to guarantee that the boot code of the external microcontroller has enough time to finish. During the

initialization phase of the system, the user’s software can disable, reconfigure, and restart the watchdog.

Disabling the watchdog before configuration is required as all write accesses to the register wdogPresetVal

and the register wdogCfg except the bits wdogLock and wdogEna (see Table 3.12) are blocked when the

watchdog is active. As it takes multiple low-power clock cycles until the enable signal is evaluated inside the

watchdog clock domain, the SSW[7] bit (wdActive) must be checked to determine if write accesses are

possible. To avoid any malfunction during reconfiguration, the prescaler registers are set to 0 and the counter

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