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CS5101 bảng dữ liệu(PDF) 3 Page - ON Semiconductor

tên linh kiện CS5101
Giải thích chi tiết về linh kiện  Secondary Side Post Regulator for AC/DC and DC/DC Multiple Output Converters
PDF  9 Pages
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nhà sản xuất  ONSEMI [ON Semiconductor]
Trang chủ  http://www.onsemi.com
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CS5101 bảng dữ liệu(HTML) 3 Page - ON Semiconductor

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CS5101
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ELECTRICAL CHARACTERISTICS (−40°C ≤ TA ≤ 85°C, −40°C ≤ TJ ≤ 150°C, 10 V < VCC < 45 V, 8.0 V < VC < 75 V; unless
otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Error Amplifier
Input Voltage Initial Accuracy
VFB = VCOMP, VCC = 15 V, T = 25°C, Note 3
1.98
2.00
2.02
V
Input Voltage
VFB = VCOMP, includes line and temp
1.94
2.00
2.06
V
Input Bias Current
VFB = 0 V, IVFB flows out of pin
−
−
500
nA
Open Loop Gain
1.5 V < VCOMP < 3.0 V
60
70
−
dB
Unity Gain Bandwidth
1.5 V < VCOMP < 3.0 V, Note 3
0.7
1.0
−
MHz
Output Sink Current
VCOMP = 2.0 V, VFB = 2.2 V
2.0
8.0
−
mA
Output Source Current
VCOMP = 2.0 V, VFB = 1.8 V
2.0
6.0
−
mA
VCOMP High
VFB = 1.8 V
3.3
3.5
3.7
V
VCOMP Low
VFB = 2.2 V
0.85
1.0
1.15
V
PSRR
10 V < VCC < 45 V, VFB = VCOMP, Note 3
60
70
−
dB
Voltage Reference
Output Voltage Initial Accuracy
VCC = 15 V, T = 25°C, Note 3
4.9
5.0
5.1
V
Output Voltage
0 A < IREF < 8.0 mA
4.8
5.0
5.2
V
Line Regulation
10 V < VCC < 45 V, IREF = 0 A
−
10
60
mV
Load Regulation
0 A < IREF < 8.0 mA
−
20
60
mV
Current Limit
VREF = 4.8 V
10
50
−
mA
VREF−OK FAULT V
VSYNC = 5.0 V, VREF = VLOAD
4.10
4.40
4.60
V
VREF−OK V
VSYNC = 5.0 V, VREF = VLOAD
4.30
4.50
4.80
V
VREF−OK Hysteresis
−
40
100
250
mV
Current Sense Amplifier
IS COMP High V
IS+ = 5.0 V, IS− = IS COMP
4.7
5.0
5.3
V
IS COMP Low V
IS+ = 0 V, IS− = IS COMP
0.5
1.0
1.3
V
Source Current
IS+ = 5.0 V, IS− = 0 V
2.0
10
−
mA
Sink Current
IS− = 5.0 V, IS+ = 0 V
10
20
−
mA
Open Loop Gain
1.5 V ≤ VCOMP ≤ 4.5 V, RL = 4.0 kW
60
80
−
dB
CMRR
Note 3
60
80
−
dB
PSRR
10 V < VCC < 45 V, Note 3
60
80
−
dB
Unity Gain Bandwidth
1.5 V ≤ VCOMP ≤ 4.5 V, RL = 4.0 kW, Note 3
0.5
0.8
−
MHz
Input Offset Voltage
VIS+ = 2.5 V, VIS− = VISCOMP
−8.0
0
8.0
mV
Input Bias Currents
VIS+ = VIS− = 0 V, IIS flows out of pins
−
20
250
nA
Input Offset Current (IS+, IS−)
−
−250
0
250
nA
Input Signal Voltage Range
Note 3
−0.3
−
VCC − 4.0
V
RAMP/SYNC Generator
RAMP Source Current Initial Accuracy
VSYNC = 5.0 V, VRAMP = 2.5 V, T = 25°C, Note 3
0.18
0.20
0.22
mA
RAMP Source Current
VSYNC = 5.0 V, VRAMP = 2.5 V
0.16
0.20
0.24
mA
RAMP Sink Current
VSYNC = 0 V, VRAMP = 2.5 V
1.0
4.0
−
mA
RAMP Peak Voltage
VSYNC = 5.0 V
3.3
3.5
3.7
V
RAMP Valley Voltage
VSYNC = 0 V
1.4
1.5
1.6
V
RAMP Dynamic Range
VRAMPDR = VRAMPPK − VRAMPVY
1.7
2.0
2.3
V
RAMP Sleep Threshold Voltage
VRAMP @ VREF < 2.0 V
0.3
0.6
1.0
V
SYNC Threshold
VSYNC @ VRAMP > 2.5 V
2.3
2.5
2.7
V
SYNC Input Bias Current
VSYNC = 0 V, ISYNC flows out of pin
−
1.0
20
mA
3. Guaranteed by design. Not 100% tested in production.



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