M24512-WDW6TP datasheet(17/31 Pages) STMICROELECTRONICS

17 / 31 page

M24512-W, M24512-R, M24256-BW, M24256-BR

Device operation

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3.11

Read Operations

Read operations are performed independently of the state of the Write Control (WC) signal.

After the successful completion of a Read operation, the device’s internal address counter is

incremented by one, to point to the next byte address.

3.12

Random Address Read

A dummy Write is first performed to load the address into this address counter (as shown in

Figure 9.) but without sending a Stop condition. Then, the bus master sends another Start

condition, and repeats the Device Select Code, with the Read/Write bit (RW) set to 1. The

device acknowledges this, and outputs the contents of the addressed byte. The bus master

must not acknowledge the byte, and terminates the transfer with a Stop condition.

3.13

Current Address Read

For the Current Address Read operation, following a Start condition, the bus master only

sends a Device Select Code with the Read/Write bit (RW) set to 1. The device

acknowledges this, and outputs the byte addressed by the internal address counter. The

counter is then incremented. The bus master terminates the transfer with a Stop condition,

as shown in Figure 9., without acknowledging the byte.

3.14

Sequential Read

This operation can be used after a Current Address Read or a Random Address Read. The

bus master does acknowledge the data byte output, and sends additional clock pulses so

that the device continues to output the next byte in sequence. To terminate the stream of

bytes, the bus master must not acknowledge the last byte, and must generate a Stop

condition, as shown in Figure 9.

The output data comes from consecutive addresses, with the internal address counter

automatically incremented after each byte output. After the last memory address, the

address counter ‘rolls-over’, and the device continues to output data from memory address

00h.

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