MAS9560 datasheet(23/25 Pages) MAS

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DA9560.001

20 January, 2005

SPI BUS TIMING

LSVDD = VBAT = 3.6V, EPVDD = HPVDD = VLDO = 2.86V (LDO-mode), -40

°C ≤ TA ≤ +85°C, typical values at TA = +27°C,

unless otherwise noted

Parameter

Name

Conditions

Min

Nom

Max

Unit

Input Low voltage

tbd

IOVDD

Input High voltage

tbd

IOVDD

Input Impedance

tbd

Input Leakage Current

SDI,

SCLK

0 V

< Input < IOVDD

tbd

µA

Input Setup Time before

clock rising edge

SDI,

XCS

Tbd

Input Hold Time after clock

falling edge

SDI,

XCS

Tbd

Output Low Voltage

SDO

ILOAD = 0.5 mA,

IOVDD = 1.8 V

tbd

Output High Voltage

SDO

ILOAD = -0.5 mA,

IOVDD = 1.8 V

tbd

Clock Frequency, read

access

SCLK,

SDI,

SDO

CLOAD = 20 pF,

IOVDD = 3.3 V

tbd

MHz

Clock Frequency, read

access

SCLK,

SDI,

SDO

CLOAD = 20 pF,

IOVDD = 1.8 V

tbd

MHz

Clock Frequency, write

access

SCLK,

SDI

CLOAD = 20 pF,

IOVDD = 3.3 V

tbd

MHz

Clock Frequency, write

access

SCLK,

SDI

CLOAD = 20 pF,

IOVDD = 1.8 V

tbd

MHz

I2S BUS TIMING

LSVDD = VBAT = 3.6V, EPVDD = HPVDD = VLDO = 2.86V (LDO-mode), -40

°C ≤ TA ≤ +85°C, typical values at TA = +27°C,

unless otherwise noted

Parameter

Name

Conditions

Min

Nom

Max

Unit

Input Low Voltage

tbd

IOVDD

Input High voltage

tbd

IOVDD

Input Impedance

tbd

Input Leakage Current

DAI,

CLI,

WSI

0 V < Input < IOVDD

tbd

µA

Input Setup Time before

clock rising edge

DAI,

WSI

tbd

Input Hold Time after clock

falling edge

DAI,

WSI

tbd

Clock Frequency (Note 1)

CLI,

DAI

tbd

MHz

Note 1: I

2S clock (CLI) frequency ratio will affect to DAC sampling in oversampling mode. See Control Register

description (p. 18)

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