PIC12F683-ESLASHP datasheet(89/148 Pages) MICROCHIP

89 / 148 page

 2004 Microchip Technology Inc.

Preliminary

DS41211B-page 87

PIC12F683

FIGURE 12-8:

INT PIN INTERRUPT TIMING

TABLE 12-6:

SUMMARY OF INTERRUPT REGISTERS

Address

Name

Bit 7Bit 6Bit 5

Bit 4Bit 3Bit 2

Bit 1Bit 0

Value on

POR, BOD

Value on

all other

Resets

0Bh, 8Bh INTCON

GIE

PEIE

T0IE

INTE

GPIE

T0IF

INTF

GPIF

0000 0000

0Ch

PIR1

EEIF

ADIF

CCP1IF

—

CMIF

OSFIF

TMR2IF

TMR1IF

000- 0000

8Ch

PIE1

EEIE

ADIE

CCP1IE

—

CMIE

OSFIE

TMR2IE TMR1IE

000- 0000

Legend:

= unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.

Shaded cells are not used by the interrupt module.

OSC1

CLKOUT(3)

INT pin

INTF Flag

(INTCON<1>)

GIE bit

(INTCON<7>)

Instruction Flow

Instruction

Fetched

Instruction

Executed

Interrupt Latency(2)

PC + 1

0004h

0005h

Inst (0004h)

Inst (0005h)

Dummy Cycle

Inst (PC)

Inst (PC + 1)

Inst (PC – 1)

Inst (0004h)

Dummy Cycle

Inst (PC)

—

Note

INTF flag is sampled here (every Q1).

Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

CLKOUT is available only in INTOSC and RC Oscillator modes.

For minimum width of INT pulse, refer to AC specifications in Section 15.0 “Electrical Specifications”.

INTF is enabled to be set any time during the Q4-Q1 cycles.

(1)

(4)

(5)

(1)

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